13904895
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Quiz von Good Guy Beket, aktualisiert more than 1 year ago
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Erstellt von Good Guy Beket
vor fast 6 Jahre
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Frage 1
Frage
What is a Latency:
Antworten
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is time for a single access – Main memory latency is usually >> than processor cycle time
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is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
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is amount of data that can be in flight at the same time (Little’s Law)
Frage 2
Frage
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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n loop iterations
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subroutine call
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vector access
Frage 3
Frage
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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subroutine call
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n loop iterations
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vector access
Frage 4
Frage
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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subroutine call
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n loop iterations
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vector access
Frage 5
Frage
Cache HIT:
Antworten
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No Write Allocate, Write Allocate
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Write Through, Write Back
Frage 6
Frage
Cache MISS:
Antworten
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No Write Allocate, Write Allocate
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Write Through, Write Back
Frage 7
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Average Memory Access Time is equal:
Antworten
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Hit Time * ( Miss Rate + Miss Penalty )
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Hit Time - ( Miss Rate + Miss Penalty )
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Hit Time / ( Miss Rate - Miss Penalty )
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Hit Time + ( Miss Rate * Miss Penalty )
Frage 8
Frage
The formula of “Iron Law” of Processor Performance:
Antworten
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time/program = instruction/program * cycles/instruction * time/cycle
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time/program = instruction/program * cycles/instruction + time/cycle
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time/program = instruction/program + cycles/instruction * time/cycle
Frage 9
Frage
Structural Hazard:
Antworten
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An instruction in the pipeline needs a resource being used by another instruction in the pipeline
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An instruction depends on a data value produced by an earlier instruction
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 10
Frage
Data Hazard:
Antworten
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An instruction depends on a data value produced by an earlier instruction
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An instruction in the pipeline needs a resource being used by another instruction in the pipeline
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 11
Frage
Control Hazard:
Antworten
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
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An instruction depends on a data value produced by an earlier instruction
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An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Frage 12
Frage
What is a Bandwidth:
Antworten
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a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
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is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Frage 13
Frage
What is a Bandwidth-Delay Product:
Antworten
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is amount of data that can be in flight at the same time (Little’s Law)
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is time for a single access – Main memory latency is usually >> than processor cycle time
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is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
Frage 14
Frage
What is Computer Architecture?
Antworten
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is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
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is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
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the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Frage 15
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Least Recently Used (LRU):
Antworten
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cache state must be updated on every access
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Used in highly associative caches
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FIFO with exception for most recently used block(s)
Frage 16
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Cache Hit -
Antworten
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Write Through – write both cache and memory, generally higher traffic but simpler to design
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Write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
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No Write Allocate – only write to main memory
Frage 17
Frage
Reduce Miss Rate: Large Cache Size.
Empirical Rule of Thumb:
Antworten
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If cache size is doubled, miss rate usually drops by about √2
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Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
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None of them
Frage 18
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Reduce Miss Rate: High Associativity.
Empirical Rule of Thumb:
Antworten
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Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
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If cache size is doubled, miss rate usually drops by about √2
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None of them
Frage 19
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What is the access time?
Antworten
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Time between when a read is requested and when the desired word arrives
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The minimum time between requests to memory.
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Describes the technology inside the memory chips and those innovative, internal organizations
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None of them
Frage 20
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What is the cycle time?
Antworten
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The minimum time between requests to memory.
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Time between when a read is requested and when the desired word arrives
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The maximum time between requests to memory.
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None of them
Frage 21
Frage
What does SRAM stands for?
Antworten
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Static Random Access memory
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System Random Access memory
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Short Random Access memory
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None of them
Frage 22
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What does DRAM stands for?
Antworten
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Dynamic Random Access memory
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Dual Random Access memory
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Dataram Random Access memory
Frage 23
Frage
Which one is concerning to fallacy?
Antworten
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Predicting cache performance of one program from another
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Simulating enough instructions to get accurate performance measures of the memory hierarchy
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Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
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Over emphasizing memory bandwidth in DRAMs
Frage 24
Frage
Which one is NOT concerning to pitfall?
Antworten
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Predicting cache performance of one program from another
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Simulating enough instructions to get accurate performance measures of the memory hierarchy
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Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
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Over emphasizing memory bandwidth in DRAMs
Frage 25
Frage
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
Antworten
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The time between when the user enters the command and the complete response is displayed
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The time for the user to enter the command
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The time from the reception of the response until the user begins to enter the next command
Frage 26
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If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
Antworten
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The time from the reception of the response until the user begins to enter the next command
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The time for the user to enter the command
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The time between when the user enters the command and the complete response is displayed
Frage 27
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Antworten
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
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Average time per task in the queue
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 28
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Antworten
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Average time per task in the queue
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 29
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time system” -
Antworten
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
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Average time per task in the queue
Frage 30
Frage
Little’s Law and a series of definitions lead to several useful equations for “Length server” -
Antworten
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Average number of tasks in service
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Average length of queue
Frage 31
Frage
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
Antworten
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Average length of queue
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Average number of tasks in service
Frage 32
Frage
Select two-dimensional interconnection network
Antworten
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Mesh
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Linear Array
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Cross Bar
Frage 33
Frage
Select multi-dimensional interconnection network
Antworten
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Linear Array
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Cross Bar
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Cube
Frage 34
Frage
Select multi-dimensional interconnection network
Antworten
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Linear Array
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Cross Bar
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Hyper Cube
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