Which of the following descriptions corresponds to static power?
Proportional to the product of the number of switching transistors and the switching rate
Grows proportionally to the transistor count (whether or not the transistors are switching)
Dominant energy consumer
All of the above
Which of the following descriptions corresponds to dynamic power?
Certainly a design concern
None of the above
Which of the written below is NOT increase power consumption?
Increasing performance
Increasing multiple cores
Increasing multithreading
Decreasing performance
Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when
The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
The number of transistors switching will be proportional to the sustained rate, and the performance is proportional to the peak issue rate
The number of transistors switching will be proportional to the sustained rate
The performance is proportional to the peak issue rate
How this process called: “Operations execute as soon as their operands are available”
data flow execution
instruction execution
data control execution
instruction field execution
If we want to sustain four instructions per clock
We must fetch less, issue more, and initiate execution on more than two instructions
We must fetch more, issue less, and initiate execution on more than three instructions
We must fetch more, issue more, and initiate execution on more than four instructions
We must fetch more, issue more, and initiate execution on less than five instructions
For what the reorder buffer is used :
To pass parameters through instructions that may be speculated
To pass results among instructions that may be speculated.
To get additional registers in the same way as the reservation stations
To control registers
How many fields contains the entry in the ROB:
5
6
3
4
Choose correct fields of entry in the ROB:
the source type, the destination field, the value field, and the ready field
the program type, the ready field, the parameter field, the destination field
the instruction type, the destination field, the value field, and the ready field
the instruction type, the destination field, and the ready field
Choose the steps of instruction execution:
issue, execute, write result, commit
execution, commit, rollback
issue, execute, override, exit
begin, write, interrupt, commit
Which Multiple-issue processors has not the hardware hazard detection:
Superscalar(dynamic)
Superscalar(static)
Superscalar(speculative)
EPIC
Examples of EPIC:
Pentium 4, MIPS R12K, IBM, Power5
Itanium
MIPS and ARM
TI C6x
Examples of superscalar(static):
If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Static power
Dynamic power
Processing rate
Processor state
Examples of superscalar(dynamic) :
None at the present
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Limited ILP due to software dependences
Achievable ILP with hardware resource constraints
Variability of ILP due to software and hardware interaction
Achievable ILP with software resource constraints
Examples of VLIW/LIW:
What is a hash table?
Popular data structure for updating large collections, so that one can hardly answer questions
Popular tables for organizing a large collection of data structure
Popular data structure for organizing a large collection of data items so that one can quickly answer questions
Popular data structure for deleting small collections of data items so that one can hardly answer questions
A branch-prediction cache that stores the predicted address for the next instruction after a branch
branch-target buffer
data buffer
framebuffer
optical buffer
Buffering the actual target instructions allows us to perform an optimization which called:
branch folding
Branch prediction
Target instructions
Target address
Which of these is NOT characteristics of recent highperformance microprocessors?
Power
Functional unit capability
Clock rate
Color
Which is not the function of integrated instruction fetch unit:
Integrated branch prediction
Instruction prefetch
Instruction memory access and buffering
Instruction memory commit
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Address aliasing prediction
Dynamic branch prediction
How to decrypt RISC?
Reduced Instruction Set Computer
Recall Instruction Sell Communication
Rename Instruction Sequence Corporation
Red Instruction Small Computer
The ideal pipeline CPI is a measure of …
the maximum performance attainable by the instruction
the minimum performance attainable by the implementation
the maximum performance attainable by the implementation
the minimum performance attainable by the instruction
what is the Pipeline CPI = ?
deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
deal pipeline CPU + Data hazard stalls + Control stalls
deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
Structural stalls + Data hazard stalls + Control stalls
The simplest and most common way to increase the ILP is …?
to exploit minimalism among iterations of a loop
to exploit parallelism among iterations of a loop
to destroy iterations of a loop
to decrease the minimalism of risk
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
exploit-level parallelism
high-level minimalism
loop-level parallelism
low-level minimalism
In parallelism have three different types of dependences, tagging him:
data dependences , name dependences , and control dependences .
data dependences , name dependences , and surname dependences .
datagram dependences , name dependences , and animal dependences .
no correct answers
What is Name dependence?
name dependence occurs when two instructions use the same register or memory location
name dependence occurs when five or more instructions use the same register or memory location
name dependence occurs when instructions use the same name
All answers is correct
When occurs an output dependence?
when i and instruction j write the same name
when i and instruction j write the same register or memory location
when i and instruction j write the same adress or memory location
What is RAW (read after write)?
when j tries to read a source before i writes it, so j incorrectly gets the old value
when i tries to read a source before j writes it, so j correctly gets the old value
when j tries to write a source before i writes it
when a tries to write a source before b read it, so a incorrectly gets the old value
What is given is not a hazard?
WAR
RAR
WAW
LOL
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
loop-level
loop rolling
loop unrolling
Effect that results from instruction scheduling in large code segments is called…?
register pressure
registration
The simplest dynamic branch-prediction scheme is a
branch-prediction buffer
branch buffer
All answers correct
Branch predictors that use the behavior of other branches to make a prediction are called
correlating predictors or two-level predictors
branch table
three level loop
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
the number of prediction entries selected by the branch = 1K.
the number of prediction entries selected by the branch = 2K.
the number of prediction entries selected by the branch = 8K.
the number of prediction entries selected by the branch = 4K.
What is the compulsory in Cs model?
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
The number of accesses that miss divided by the number of accesses.
None of these
What is capacity in Cs model?
What is conflict in Cs model?
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
Choose the benefit of Cache Optimization.
Larger block size to reduce miss rate
Bigger caches to increase miss rat
Single level caches to reduce miss penalty
Choose the strategy of Seventh Optimization.
Critical word first
Critical restart
Sequential interleaving
Merging Write Buffer to Reduce Miss Penalty
Choose the Eight Optimization
Nonblocking Caches to Increase Cache Bandwidth
Trace Caches to Reduce Hit Time
Choose the Eleventh Optimization
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
What is the access time?
Time between when a read is requested and when the desired word arrives
The minimum time between requests to memory.
Describes the technology inside the memory chips and those innovative, internal organizations
9. What is the cycle time?
The maximum time between requests to memory.
What does SRAM stands for?
Static Random Access memory
System Random Access memory
Short Random Access memory
What does DRAM stands for?
Dynamic Random Access memory
Dual Random Access memory
Dataram Random Access memory
What does DDR stands for?
Double data rate
Dual data rate
Double data reaction
What is kernel process?
Provide at least two modes, indicating whether the running process is a user process or an operating system process
Provide at least five modes, indicating whether the running process is a user process or an operating system process
Provide a portion of the processor state that a user process can use but not write
Which one is NOT concerning to pitfall?
Simulating enough instructions to get accurate performance measures of the memory hierarchy
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
Overemphasizing memory bandwidth in DRAMs
Predicting cache performance of one program from another
Which one is concerning to fallacy?
