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PCA_Final [arc2-1, Part-1]

Question 1 of 128

1

Storage Systems, “Higher associativity to reduce miss rate”

Select one of the following:

  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

  • The obvious way to reduce capacity misses is to increase cache capacity

  • Obviously, increasing associativity reduces conflict misses

Explanation

Question 2 of 128

1

How many Optimizations’ in Cache memory Performance?

Select one of the following:

  • 6

  • 8

  • 10

Explanation

Question 3 of 128

1

Storage Systems, “Larger block size to reduce miss rate”

Select one of the following:

  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

  • The obvious way to reduce capacity misses is to increase cache capacity

  • Obviously, increasing associativity reduces conflict misses

Explanation

Question 4 of 128

1

What is the “Read Operands” in simple five-stage pipeline?

Select one of the following:

  • Wait until no data hazards, then reads the operand

  • Decode instructions, check for structural hazards

Explanation

Question 5 of 128

1

Storage Systems, “Bigger caches to reduce miss rate”

Select one of the following:

  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

  • The obvious way to reduce capacity misses is to increase cache capacity

  • Obviously, increasing associativity reduces conflict misses

Explanation

Question 6 of 128

1

Tenth optimization of Cache Memory “Register prefetch”?

Select one of the following:

  • Loads data only into the cache and not the register

  • Will load the value into register

Explanation

Question 7 of 128

1

At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”?

Select one of the following:

  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

  • Faults in software (usually) and hardware design (occasionally)

  • Mistakes by operations and maintenance personnel

Explanation

Question 8 of 128

1

What is a “Kernel” in Cache Memory?

Select one of the following:

  • Execution or waiting for synchronization variables

  • Execution in user code

  • Execution in the OS that is neither idle nor in synchronization access

Explanation

Question 9 of 128

1

Little’s Law and a series of definitions lead to several useful equations for “Time queue” -

Select one of the following:

  • Average time per task in the queue

  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Explanation

Question 10 of 128

1

How many steps took Virtual Machine Monitor to improve performance of virtual machines?

Select one of the following:

  • 5

  • 3

  • 4

Explanation

Question 11 of 128

1

How many issue queue used in Centralized Superscalar 2 and Exceptions

Select one of the following:

  • 4

  • 3

  • 2

  • 1

Explanation

Question 12 of 128

1

Which of the following formula is true about Issue Queue for “Instruction Ready”

Select one of the following:

  • Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards

  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards

  • Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards

  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards

Explanation

Question 13 of 128

1

What is the “Read Operands” in Pipelining Basics?

Select one of the following:

  • Wait until no control hazards, then reads the operand

  • Wait until no structural hazards, then reads the operand

  • Wait until no data hazards, then reads the operand

Explanation

Question 14 of 128

1

Perfect caches at The Hardware Model?

Select one of the following:

  • All memory accesses take one clock cycle

  • All conditional branches are predicted exactly

  • All memory addresses are known exactly

Explanation

Question 15 of 128

1

How many stages used in Superscalar (Pipeline)?

Select one of the following:

  • 4

  • 5

  • 6

  • 7

Explanation

Question 16 of 128

1

How much in percentage single-processor performance improvement has dropped to less than?

Select one of the following:

  • 22%

  • 33%

  • 11%

Explanation

Question 17 of 128

1

What is “VLIW”?

Select one of the following:

  • Very Long Instruction Word

  • Very Less Interpreter Word

  • Very Light Internal Word

  • Very Low Invalid Word

Explanation

Question 18 of 128

1

At VLIW by “performance and loop iteration” which time is shorter?

Select one of the following:

  • Software Pipelined

  • Loop Unrolled

Explanation

Question 19 of 128

1

Little’s Law and a series of definitions lead to several useful equations for “Time server” -

Select one of the following:

  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

  • Average time per task in the queue

  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Explanation

Question 20 of 128

1

What single-processor performance improvement has dropped?

Select one of the following:

  • 2004

  • 2002

  • 2003

Explanation

Question 21 of 128

1

What does MAF?

Select one of the following:

  • Miss Address File

  • Map Address File

  • Memory Address File

Explanation

Question 22 of 128

1

How many classes of computers classified?

Select one of the following:

  • 3

  • 5

  • 7

Explanation

Question 23 of 128

1

Sixth Optimization of Cache Memory “Critical word first”?

Select one of the following:

  • Fetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution

  • Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Explanation

Question 24 of 128

1

In an important early study of intrusion, Anderson[ANDE80] identified three classes of intruders:

Select one of the following:

  • Control, exploit, system

  • Masquerader, misfeasor, clandestine user

  • Individual, legitimate, authorized

  • Outside, inside, offside

Explanation

Question 25 of 128

1

How many elements of the Instruction Set Architecture (ISA):

Select one of the following:

  • 7

  • 8

Explanation

Question 26 of 128

1

What is the “Bigger caches to reduce miss rate” at Basics of Memory Hierarchies

Select one of the following:

  • The obvious way to reduce capacity misses is to increase cache capacity

  • Obviously, increasing associativity reduces conflict misses

Explanation

Question 27 of 128

1

At storage systems Gray and Siewiorek classify faults what does mean “Design faults”?

Select one of the following:

  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

  • Faults in software (usually) and hardware design (occasionally)

  • Mistakes by operations and maintenance personnel

Explanation

Question 28 of 128

1

What is the ARF?

Select one of the following:

  • Architectural Register File

  • Architecture Relocation File

  • Architecture Reload File

  • Architectural Read File

Explanation

Question 29 of 128

1

What is the Conflict in main categories in Cache Memory?

Select one of the following:

  • first-reference to a block, occur even with infinite cache

  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Explanation

Question 30 of 128

1

Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is?

Select one of the following:

  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time

  • CPU time-Cache Miss-Miss Penalty-CPU time

  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Explanation

Question 31 of 128

1

At VLIW “Superscalar Control Logic Scaling” which parameters are used?

Select one of the following:

  • Width and Lifetime

  • Width and Height

  • Time and Cycle

  • Length and Addition

Explanation

Question 32 of 128

1

What is a “Synchronization” in Cache Memory?

Select one of the following:

  • Execution in the OS that is neither idle nor in synchronization access

  • Execution in user code

  • Execution or waiting for synchronization variables

Explanation

Question 33 of 128

1

Non-Blocking Cache Timeline for “Blocking Cache” the sequence is?

Select one of the following:

  • CPU time-Cache Miss-Miss Penalty-CPU time

  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Explanation

Question 34 of 128

1

Flash memory is a type of?

Select one of the following:

  • Electronically Erasable Programmable Read-Only Memory

  • Electronically Extensible Programmable Re-Order Memory

  • Electronically Executable Programmable Reduce Memory

Explanation

Question 35 of 128

1

Access time at memory latency is -

Select one of the following:

  • The time between when a read is requested and when the desired word arrives

  • The minimum time between unrelated requests to memory

Explanation

Question 36 of 128

1

In Multilevel Caches “Local miss rate” equals =

Select one of the following:

  • misses in cache / accesses to cache

  • misses in cache / CPU memory accesses

  • misses in cache / number of instructions

Explanation

Question 37 of 128

1

What is a RAID 1?

Select one of the following:

  • Also called mirroring or shadowing, there are two copies of every piece of data

  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array

  • This organization was inspired by applying memory-style error correcting codes to disks

Explanation

Question 38 of 128

1

RAW (read after write)?

Select one of the following:

  • This hazard corresponds to an output dependence

  • This hazard is the most common type and corresponds to a true data dependence

  • This hazard arises n antidependence (or name dependence)

Explanation

Question 39 of 128

1

How many size of Cache L3 is true approximately?

Select one of the following:

  • 3 MB

  • 256 MB

  • 256 KB

Explanation

Question 40 of 128

1

What is a RAID 3?

Select one of the following:

  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed

  • Many applications are dominated by small accesses

  • Also called mirroring or shadowing, there are two copies of every piece of data

Explanation

Question 41 of 128

1

What is the increasing cache bandwidth?

Select one of the following:

  • Critical word first and merging write buffer

  • Pipelined caches, multibanked caches and non-blocking caches

  • Small and simple first-level caches and way-prediction

Explanation

Question 42 of 128

1

What is RAID 2?

Select one of the following:

  • This organization was inspired by applying memory-style error correcting codes to disks

  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array

  • Also called mirroring or shadowing, there are two copies of every piece of data

Explanation

Question 43 of 128

1

In Non-Blocking Caches what does mean “Critical word first”?

Select one of the following:

  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

Explanation

Question 44 of 128

1

Sixth optimization of cache memory “Early restart”?

Select one of the following:

  • Fetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution

  • Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Explanation

Question 45 of 128

1

How many size of Cache L2 is true approximately?

Select one of the following:

  • 256 KB

  • 4 KB

  • 32 MB

Explanation

Question 46 of 128

1

Reducing the miss penalty or miss rate via parallelism?

Select one of the following:

  • Hardware prefetching and compiler prefetching

  • Compiler optimization

  • Pipelined caches, multibanked caches and non-blocking caches

Explanation

Question 47 of 128

1

What is a RT?

Select one of the following:

  • Rename Table

  • Recall Table

  • Relocate Table

  • Remove Table

Explanation

Question 48 of 128

1

How many functions at integrated instruction fetch units?

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 49 of 128

1

What is the PMD in computer classes?

Select one of the following:

  • Percentage map device

  • Personal mobile device

  • Powerful markup distance

  • Peak maze development

Explanation

Question 50 of 128

1

The second type of dependence is?

Select one of the following:

  • Data dependence

  • Name dependence

  • Control dependence

Explanation

Question 51 of 128

1

How many elements presented at performance trends: bandwidth over latency?

Select one of the following:

  • 4

  • 5

  • 3

Explanation

Question 52 of 128

1

What is the compulsory in main categories in cache memory?

Select one of the following:

  • Cache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)

  • Misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

  • First-reference to a block, occurs even with infinite cache

Explanation

Question 53 of 128

1

How many elements in trends of technology?

Select one of the following:

  • 5

  • 4

  • 6

Explanation

Question 54 of 128

1

Perfect memory address alias analysis at the Hardware model?

Select one of the following:

  • All conditional branches are predicted exactly

  • All memory accesses take one clock cycle

  • All memory addresses are known exactly

Explanation

Question 55 of 128

1

Speculating on exceptions “Recovery mechanism” is –

Select one of the following:

  • Exceptions are rare, so simply predicting no exceptions is very accurate

  • Only write architectural state at commit point, so can throw away partially executed instructions after exception

  • None of them

  • An entity capable of accessing objects

Explanation

Question 56 of 128

1

What is the reducing the miss rate?

Select one of the following:

  • What is the reducing the miss rate?

  • Performance optimization

  • Compiler optimization

  • Time optimization

Explanation

Question 57 of 128

1

DDR is –

Select one of the following:

  • Double data rate

  • Density data rate

  • Dynamic data rate

Explanation

Question 58 of 128

1

In Non-blocking caches what does mean “Early restart”?

Select one of the following:

  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Explanation

Question 59 of 128

1

Which distance of price has clusters/warehouse-scale computers?

Select one of the following:

  • 100-100 000$

  • 100 000-200 000 000$

  • 5 000 -10 000 000$

Explanation

Question 60 of 128

1

Little’s Law and a series of definitions lead to several useful equations for “Time System”-

Select one of the following:

  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

  • Average time per task in the queue

Explanation

Question 61 of 128

1

What is the MISD one of the categories of computers?

Select one of the following:

  • Multiple instructions streams, set data stream

  • Multiple instructions streams, single data stream

  • Multiple instruction stream, multiple data streams

Explanation

Question 62 of 128

1

What is a RAID 4?

Select one of the following:

  • Many applications are dominated by small accesses

  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed

  • Also called mirroring or shadowing, there are two copies of every piece of data

Explanation

Question 63 of 128

1

Tenth Optimization of cache memory “Cache prefetch”?

Select one of the following:

  • Will load the value into a register

  • Loads data only into the cache and not the register

Explanation

Question 64 of 128

1

What is the Request level parallelism?

Select one of the following:

  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.

  • Exploits parallelism among largely decoupled tasks specified by the programmer or the operating system

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Explanation

Question 65 of 128

1

Non-blocking cache timeline for “Hit under miss” the sequence is -?

Select one of the following:

  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

  • CPU time-Cache Miss-Miss Penalty-CPU time

  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Explanation

Question 66 of 128

1

At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”?

Select one of the following:

  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

  • Faults in software (usually) and hardware design (occasionally)

  • Mistakes by operations and maintenance personnel

Explanation

Question 67 of 128

1

WAR(write after read)?

Select one of the following:

  • This hazard correspond to an output dependence

  • This hazard arises from an antidependence (or name dependence)

Explanation

Question 68 of 128

1

Main term of dependability is SLAs?

Select one of the following:

  • Scale level approach

  • Service level agreements

  • Standard level achievement

Explanation

Question 69 of 128

1

At VLIW by “performance and loop iteration” which time is longer?

Select one of the following:

  • Loop unrolled

  • Software Pipelined

Explanation

Question 70 of 128

1

What is the temporal locality?

Select one of the following:

  • Exploit by remembering the contents of recently accessed locations

  • Exploit by fetching blocks of data around recently accessed locations

Explanation

Question 71 of 128

1

What is an IQ?

Select one of the following:

  • Issue Queue

  • Internal Queue

  • Interrupt Queue

  • Instruction Queue

Explanation

Question 72 of 128

1

If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time”-?

Select one of the following:

  • The time between when the user enters the command and the complete response is displayed

  • The time for the user to enter the command

  • The time from the reception of the response until the user begins to enter the next command

Explanation

Question 73 of 128

1

How many size of Cache L1 is true approximately?

Select one of the following:

  • 8 KB

  • 256 KB

  • 2 MB

Explanation

Question 74 of 128

1

What is a RISC computers?

Select one of the following:

  • Reduced instruction set computer

  • Research interconnect several computer

  • Rational interruptible security computer

Explanation

Question 75 of 128

1

The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?

Select one of the following:

  • 4

  • 6

  • 5

Explanation

Question 76 of 128

1

What is the “opcode”?

Select one of the following:

  • Operand code

  • Optional code

  • Operation code

Explanation

Question 77 of 128

1

WAW(write after write)?

Select one of the following:

  • This hazard arises from an antidependence (or name dependence)

  • This hazard corresponds to an output dependence

  • This hazard is the most common type and corresponds to a true data dependence

Explanation

Question 78 of 128

1

What is the Vector Architectures and graphic processor units(GPUs)?

Select one of the following:

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution

Explanation

Question 79 of 128

1

Speculating on exceptions “Check prediction mechanism” is –

Select one of the following:

  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

  • Exceptions are rare, so simply predicting no exceptions is very accurate

  • The way in which an object is accessed by a subject

  • None of them

Explanation

Question 80 of 128

1

At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:

Select one of the following:

  • Speculative operations that don’t cause exceptions

  • Hardware to check pointer hazards

Explanation

Question 81 of 128

1

At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:

Select one of the following:

  • Speculative operations that don’t cause exceptions

  • Hardware to check pointer hazards

Explanation

Question 82 of 128

1

What is PRF?

Select one of the following:

  • Pipeline Register File

  • Physical Register File

  • Pure Register File

  • Pending Register File

Explanation

Question 83 of 128

1

Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?

Select one of the following:

  • 3

  • 4

  • 2

Explanation

Question 84 of 128

1

How many instructions used in Distributed Superscalar 2 and Exceptions?

Select one of the following:

  • 1

  • 2

  • 3

  • 4

Explanation

Question 85 of 128

1

What is about Superscalar means “F-D-X-M-W”?

Select one of the following:

  • Fetch, Decode, Instruct, Map, Write

  • Fetch, Decode, Excite, Memory, Write

  • Fetch, Decode, Except, Map, Writeback

  • Fetch, Decode, Execute, Memory, Writeback

Explanation

Question 86 of 128

1

SDRAM is -

Select one of the following:

  • Synchronous dynamic random access memory

  • Static dynamic random access memory

  • Super dynamic random access memory

Explanation

Question 87 of 128

1

How many restrictions RAW hazards through memory are maintained?

Select one of the following:

  • 3

  • 4

  • 2

Explanation

Question 88 of 128

1

In Multilevel Caches “Misses per instruction” equals =

Select one of the following:

  • Misses in cache / number of instructions

  • Misses in cache / accesses to cache

  • Misses in cache / CPU memory accesses

Explanation

Question 89 of 128

1

How many possible Elements of Data Hazards?

Select one of the following:

  • 3

  • 6

  • 8

Explanation

Question 90 of 128

1

If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” ?

Select one of the following:

  • The time from the reception of the response until the user begins to enter the next command

  • The time for the user to enter the command

  • The time between when the user enters the command and the complete response is displayed

Explanation

Question 91 of 128

1

Clock cycle time is -

Select one of the following:

  • Hardware technology and organization

  • Organization and instruction set architecture

  • Instruction set architecture and compiler technology

Explanation

Question 92 of 128

1

A virus classification by target includes the following categories. What is a File infector?

Select one of the following:

  • The key is stored with the virus

  • Far more sophisticated techniques are possible

  • A typical approach is as follows

  • Infects files that the operating system or shell consider to be executable

Explanation

Question 93 of 128

1

What is an ALAT?

Select one of the following:

  • Addition Long Accessibility Table

  • Allocated Link Address Table

  • Allowing List Address Table

  • Advanced Load Address Table

Explanation

Question 94 of 128

1

CPI is -

Select one of the following:

  • Hardware technology and organization

  • Organization and instruction set architecture

  • Instruction set architecture and compiler technology

Explanation

Question 95 of 128

1

What is SB?

Select one of the following:

  • Scaleboard

  • Scoreboard

  • Scorebased

  • Scalebit

Explanation

Question 96 of 128

1

At Critical Word First for miss penalty chose correct sequence of Basic Blocking Cache “Order of fill”:

Select one of the following:

  • 0,1,2,3,4,5,6,7

  • 3,4,5,6,7,0,1,2

Explanation

Question 97 of 128

1

At Critical Word First for miss penalty chose correct sequence of Blocking Cache with critical word first “Order of fill”:

Select one of the following:

  • 0,1,2,3,4,5,6,7

  • 3,4,5,6,7,0,1,2

Explanation

Question 98 of 128

1

What is a RAID 0?

Select one of the following:

  • This organization was inspired by applying memory-style errorcorrecting codes to disks

  • it has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array

  • Also called mirroring or shadowing, there are two copies of every piece of data

Explanation

Question 99 of 128

1

What is a file?

Select one of the following:

  • It is the basic element of data

  • it is a collection of related fields that can be treated as a unit by some application program

  • it is a collection of related data

  • it is a collection of similar records

Explanation

Question 100 of 128

1

What is the reducing the miss penalty?

Select one of the following:

  • Pipelined caches, multibanked caches, and nonblocking caches

  • Critical word first and merging write buffer

  • Small and simple first-level caches and way-prediction

Explanation

Question 101 of 128

1

Little’s Law and a series of definitions lead to several useful equations for “length server”-:

Select one of the following:

  • Average length of queue

  • Average number of tasks in service

Explanation

Question 102 of 128

1

At storage systems gray and Siewiorek classify faults what does mean “environmental faults”?

Select one of the following:

  • Fire, flood, earthquake, power failure and sabotage

  • Faults in software (usually) and hardware design (occasionally)

  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Explanation

Question 103 of 128

1

How many types of dependencies do you know?

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 104 of 128

1

How many major flavors in multiple-issue processors?

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 105 of 128

1

Out-of-order control complexity MIPS R10000 which is not in control logic?

Select one of the following:

  • CLK

  • Address queue

  • Integer datapath

  • Free list

Explanation

Question 106 of 128

1

At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches

Select one of the following:

  • Allow one instruction to branch multiple directions

  • Speculative operations that don’t cause exceptions

Explanation

Question 107 of 128

1

Infinite register renaming at the hardware model?

Select one of the following:

  • There are an infinite number of virtual registers available

  • Branch prediction is perfect, all conditional branches are predicted exactly

Explanation

Question 108 of 128

1

What is reducing hit time?

Select one of the following:

  • Pipelined caches, multibanked caches, and nonblocking caches

  • Critical word first and merging write buffer

  • Small and simple first-level caches and way-prediction

Explanation

Question 109 of 128

1

Cycle time at memory latency is -

Select one of the following:

  • The time between when a read is requested and when the desired word arrives

  • the minimum time between unrelated requests to memory

Explanation

Question 110 of 128

1

Speculating on Exceptions “Prediction mechanism” is

Select one of the following:

  • None of them

  • exceptions are rare, so simply predicting no exceptions is very accurate

  • only write architecture state at commit point, so can throw away partially executed instructions after exception

  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

Explanation

Question 111 of 128

1

How many main levels of cache memory?

Select one of the following:

  • 2

  • 8

  • 3

  • 6

Explanation

Question 112 of 128

1

What is the thread level parallelism -

Select one of the following:

  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Explanation

Question 113 of 128

1

How many steps in instruction execution?

Select one of the following:

  • 4

  • 6

  • 3

  • 5

Explanation

Question 114 of 128

1

How many issue queue used in Centralized Superscalar 2 and exceptions?

Select one of the following:

  • 2

  • 4

  • 3

  • 1

Explanation

Question 115 of 128

1

What is a FL?

Select one of the following:

  • free leg

  • free list

  • free last

  • free launch

Explanation

Question 116 of 128

1

If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time”-?

Select one of the following:

  • The time from the reception of the response until the user begins to enter the next command

  • the time between when the user enters the command and the complete response is displayed

  • the time for the user to enter the command

Explanation

Question 117 of 128

1

What is the “issue” in pipelining basics?

Select one of the following:

  • Decode instructions, check for data hazard

  • Decode instructions, check for control hazard

  • Decode instructions, check for structural hazard

Explanation

Question 118 of 128

1

Little’s Law and a series of definitions lead to several useful equations for “Length queue”

Select one of the following:

  • Average length of queue

  • Average number of tasks in service

Explanation

Question 119 of 128

1

Perfect jump prediction at The Hardware Model?

Select one of the following:

  • All jumps are perfectly predicted

  • All memory addresses are known exactly

  • Branch prediction is perfect

Explanation

Question 120 of 128

1

What is the term of dependability in SLOs?

Select one of the following:

  • Standard Level Offset

  • Standard Level Objectives

Explanation

Question 121 of 128

1

What is a FSB?

Select one of the following:

  • Finished store Buffer

  • Finished stack Buffer

  • Finished star Buffer

  • Finished stall Buffer

Explanation

Question 122 of 128

1

Out-of-order control complexity MIPS R10000 which is in control logic?

Select one of the following:

  • Data tags

  • Register name

  • Instruction cache

  • Data cache

Explanation

Question 123 of 128

1

Instruction count is –

Select one of the following:

  • Organization and instruction set architecture

  • Hardware technology and organization

  • Instruction set architecture and compiler technology

Explanation

Question 124 of 128

1

What is the Instruction Level Parallelism?

Select one of the following:

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Explanation

Question 125 of 128

1

What is the RLP?

Select one of the following:

  • Random Level Parallelism

  • Request Level Parallelism

  • Research Level Parallelism

Explanation

Question 126 of 128

1

In multilevel caches “Global miss rate” equals:

Select one of the following:

  • misses in cache / CPU memory accesses

  • misses in cache / accesses to cache

  • misses in cache / number of instructions

Explanation

Question 127 of 128

1

What does mean MSHR?

Select one of the following:

  • Miss Status Handling Register

  • Memory status handling register

  • mips status hardware prefetching

  • map status handling reload

Explanation

Question 128 of 128

1

What is the spatial locality?

Select one of the following:

  • Exploit by remembering the contents of recently accessed locations

  • Exploit by fetching blocks of data around recently accessed locations

Explanation

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