11797704
Descripción
Test por Hello World, actualizado hace más de 1 año
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Creado por Hello World
hace más de 6 años
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Pregunta 1
Pregunta
109. What is a “Kernel” in Cache Memory?
Respuesta
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution or waiting for synchronization variables
-
o Execution in user code
Pregunta 2
Pregunta
108. What is a “Synchronization” in Cache Memory?
Respuesta
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution in user code
-
o Execution or waiting for synchronization variables
Pregunta 3
Pregunta
107. How many main levels of Cache Memory?
Respuesta
-
3
-
2
-
6
-
8
Pregunta 4
Pregunta
106. How many size of Cache L3 is true approximately? :
Respuesta
-
o 3 MB
-
o 256 KB
-
o 256 MB
Pregunta 5
Pregunta
105. How many size of Cache L2 is true approximately? :
Respuesta
-
o 256 KB
-
o 4 KB
-
o 32 MB
Pregunta 6
Pregunta
104. How many size of Cache L1 is true approximately? :
Respuesta
-
o 8 KB
-
o 256 KB
-
o 2 MB
Pregunta 7
Pregunta
103. Little’s Law and a series of definitions lead to several useful equations for
Respuesta
-
o Average length of queue
-
o Average number of tasks in service
Pregunta 8
Pregunta
102. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Respuesta
-
o Average number of tasks in service
-
o Average length of queue
Pregunta 9
Pregunta
101. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Respuesta
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
Pregunta 10
Pregunta
100. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Respuesta
-
o Average time per task in the queue
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 11
Pregunta
99. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Respuesta
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 12
Pregunta
98. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Respuesta
-
o The time from the reception of the response until the user begins to enter the next command
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
Pregunta 13
Pregunta
97. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Respuesta
-
o The time between when the user enters the command and the complete response is displayed
-
o The time for the user to enter the commando The time for the user to enter the command
-
o The time from the reception of the response until the user begins to enter the next command
Pregunta 14
Pregunta
96. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” - ? :
Respuesta
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
-
o The time from the reception of the response until the user begins to enter the next command
Pregunta 15
Pregunta
95. At storage systems Gray and Siewiorek classify faults what does mean “Environmental faults”? :
Respuesta
-
o Fire, flood, earthquake, power failure, and sabotage
-
o Faults in software (usually) and hardware design (occasionally)
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Pregunta 16
Pregunta
94. At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”? :
Respuesta
-
o Mistakes by operations and maintenance personnel
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
o Faults in software (usually) and hardware design (occasionally)
Pregunta 17
Pregunta
93. At storage systems Gray and Siewiorek classify faults what does mean “Design faults”? :
Respuesta
-
o Faults in software (usually) and hardware design (occasionally)
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
o Mistakes by operations and maintenance personnel
Pregunta 18
Pregunta
92. At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”? :
Respuesta
-
o Faults in software (usually) and hardware design (occasionally)
-
o Mistakes by operations and maintenance personnel
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Pregunta 19
Pregunta
91. What is a RAID 4?
Respuesta
-
o Many applications are dominated by small accesses
-
o Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 20
Pregunta
90. What is a RAID 3?
Respuesta
-
o Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
o Many applications are dominated by small accesses
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 21
Pregunta
89. What is a RAID 2?
Respuesta
-
o This organization was inspired by applying memory-style error correcting codes to disks
-
o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 22
Pregunta
88. What is a RAID 1?
Respuesta
-
o Also called mirroring or shadowing, there are two copies of every piece of data
-
o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
o This organization was inspired by applying memory-style error correcting codes to disks
Pregunta 23
Pregunta
87. What is a RAID 0?
Respuesta
-
o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
o Also called mirroring or shadowing, there are two copies of every piece of data
-
o This organization was inspired by applying memory-style error correcting codes to disks
Pregunta 24
Pregunta
86. A virus classification by target includes the following categories, What is a File infector?
Respuesta
-
o Infects files that the operating system or shell consider to be executable
-
o A typical approach is as follows
-
o The key is stored with the virus
-
o Far more sophisticated techniques are possible
Pregunta 25
Pregunta
85. In Non-Blocking Caches what does mean “Early restart”?
Respuesta
-
o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
-
o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Pregunta 26
Pregunta
84. In Non-Blocking Caches what does mean “Critical Word First”?
Respuesta
-
o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
-
o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Pregunta 27
Pregunta
83. Storage Systems, “Higher associativity to reduce miss rate” -
Respuesta
-
o Obviously, increasing associativity reduces conflict misses
-
o The obvious way to reduce capacity misses is to increase cache capacity
-
o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Pregunta 28
Pregunta
82. Storage Systems, “Bigger caches to reduce miss rate” -
Respuesta
-
o The obvious way to reduce capacity misses is to increase cache capacity
-
o Obviously, increasing associativity reduces conflict misses
-
o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Pregunta 29
Pregunta
81. Storage Systems, “Larger block size to reduce miss rate” -
Respuesta
-
o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
-
o The obvious way to reduce capacity misses is to increase cache capacity
-
o Obviously, increasing associativity reduces conflict misses
Pregunta 30
Pregunta
80. At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first “Order of fill”:
Respuesta
-
o 3,4,5,6,7,0,1,2
-
o 0,1,2,3,4,5,6,7
Pregunta 31
Pregunta
79. At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
Respuesta
-
o 0,1,2,3,4,5,6,7
-
o 3,4,5,6,7,0,1,2
Pregunta 32
Pregunta
78. What does MAF?
Respuesta
-
o Miss Address File
-
o Map Address File
-
o Memory Address File
Pregunta 33
Pregunta
77. What does mean MSHR?
Respuesta
-
o Miss Status Handling Register
-
o Map Status Handling Reload
-
o Mips Status Hardware Register
-
o Memory Status Handling Register
Pregunta 34
Pregunta
76. Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
Respuesta
-
o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
-
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
o CPU time-Cache Miss-Miss Penalty-CPU time
Pregunta 35
Pregunta
75. Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Respuesta
-
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
-
o CPU time-Cache Miss-Miss Penalty-CPU time
Pregunta 36
Pregunta
74. Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
Respuesta
-
o CPU time-Cache Miss-Miss Penalty-CPU time
-
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Pregunta 37
Pregunta
73. In Multilevel Caches “Misses per instruction” equals =
Respuesta
-
o misses in cache / number of instructions
-
o misses in cache / accesses to cache
-
o misses in cache / CPU memory accesses
Pregunta 38
Pregunta
72. In Multilevel Caches “Global miss rate” equals =
Respuesta
-
o misses in cache / CPU memory accesses
-
o misses in cache / accesses to cache
-
o misses in cache / number of instructions
Pregunta 39
Pregunta
71. In Multilevel Caches “Local miss rate” equals =
Respuesta
-
o misses in cache / accesses to cache
-
o misses in cache / number of instructions
-
o misses in cache / CPU memory accesses
Pregunta 40
Pregunta
70. What is a Conflict?
Respuesta
-
o misses that occur because of collisions due to less than full associativity
-
o first-reference to a block, occur even with infinite cache
-
o cache is too small to hold all data needed by program, occur even under perfect replacement policy
Pregunta 41
Pregunta
67. At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Respuesta
-
o Allow one instruction to branch multiple directions
-
o Speculative operations that don’t cause exceptions
Pregunta 42
Pregunta
66. What is an ALAT? :
Respuesta
-
o Advanced Load Address Table
-
o Allocated Link Address Table
-
o Allowing List Address Table
-
o Addition Long Accessibility Table
Pregunta 43
Pregunta
65. h Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Respuesta
-
o Hardware to check pointer hazards
-
o Speculative operations that don’t cause exceptions
Pregunta 44
Pregunta
64. At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Respuesta
-
o Speculative operations that don’t cause exceptions
-
o Hardware to check pointer hazards
Pregunta 45
Pregunta
63. At VLIW by “performance and loop iteration” which time is shorter?
Respuesta
-
o Software Pipelined
-
o Loop Unrolled
Pregunta 46
Pregunta
62. At VLIW by “performance and loop iteration” which time is longer?
Respuesta
-
o Loop Unrolled
-
o Software Pipelined
Pregunta 47
Pregunta
61. What is “VLIW”?
Respuesta
-
o Very Long Instruction Word
-
o Very Light Internal Word
-
o Very Less Interpreter Word
-
o Very Low Invalid Word
Pregunta 48
Pregunta
60. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Respuesta
-
o Integer Datapath
-
o CLK
-
o Free List
-
o Address Queue
Pregunta 49
Pregunta
59. Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Respuesta
-
o Register name
-
o Instruction cache
-
o Data tags
-
o Data cache
Pregunta 50
Pregunta
58. At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Respuesta
-
o Width and Lifetime
-
o Width and Height
-
o Time and Cycle
-
o Length and Addition
Pregunta 51
Pregunta
57. What is an IQ?
Respuesta
-
o Issue Queue
-
o Internal Queue
-
o Interrupt Queue
-
o Instruction Queue
Pregunta 52
Pregunta
56. What is a FL?
Respuesta
-
o Free List
-
o Free Last
-
o Free Launch
-
o Free Leg
Pregunta 53
Pregunta
55. What is a RT?
Respuesta
-
o Rename Table
-
o Recall Table
-
o Relocate Table
-
o Remove Table
Pregunta 54
Pregunta
54. Speculating on Exceptions “Recovery mechanism” is -
Respuesta
-
o Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o An entity capable of accessing objects
-
o None of them
Pregunta 55
Pregunta
1. Speculating on Exceptions “Check prediction mechanism” is -
Respuesta
-
o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o The way in which an object is accessed by a subject
-
o None of them
Pregunta 56
Pregunta
52. Speculating on Exceptions “Prediction mechanism” is -
Respuesta
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
o Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
o None of them
Pregunta 57
Pregunta
51. What is about Superscalar means “F-D-X-M-W”?
Respuesta
-
o Fetch, Decode, Execute, Memory, Writeback
-
o Fetch, Decode, Instruct, Map, Write
-
o Fetch, Decode, Excite, Memory, Write
-
o Fetch, Decode, Except, Map, Writeback
Pregunta 58
Pregunta
50. How many stages used in Superscalar (Pipeline)?
Respuesta
-
5
-
4
-
6
-
7
Pregunta 59
Pregunta
49. What is a SB?
Respuesta
-
o Scoreboard
-
o Scorebased
-
o Scalebit
-
o Scaleboard
Pregunta 60
Pregunta
48. What is a PRF?
Respuesta
-
o Physical Register File
-
o Pending Register File
-
o Pipeline Register File
-
o Pure Register File
Pregunta 61
Pregunta
47. What is a FSB?
Respuesta
-
o Finished Store Buffer
-
o Finished Stack Buffer
-
o Finished Stall Buffer
-
o Finished Star Buffer
Pregunta 62
Pregunta
46. What is a ROB?
Respuesta
-
o Reorder Buffer
-
o Read Only Buffer
-
o Reload Buffer
-
o Recall Buffer
Pregunta 63
Pregunta
45. What is a ARF:
Respuesta
-
o Architectural Register File
-
o Architecture Relocation File
-
o Architecture Reload File
-
o Architectural Read File
Pregunta 64
Pregunta
44. Which of the following formula is true about Issue Queue for “Instruction Ready”:
Respuesta
-
o Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
-
o Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
-
o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
-
o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
Pregunta 65
Pregunta
43. How many instructions used in Distributed Superscalar 2 and Exceptions?
Respuesta
-
4
-
3
-
2
-
1
Pregunta 66
Pregunta
42. How many issue queue used in Distributed Superscalar 2 and Exceptions:
Respuesta
-
4
-
3
-
2
-
1
Pregunta 67
Pregunta
41. How many issue queue used in Centralized Superscalar 2 and Exceptions?
Respuesta
-
4
-
3
-
2
-
1
Pregunta 68
Pregunta
40. Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
Respuesta
-
o Average length of queue
-
o Average number of tasks in service
Pregunta 69
Pregunta
39. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Respuesta
-
o Average number of tasks in service
-
o Average length of queue
Pregunta 70
Pregunta
38. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Respuesta
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
Pregunta 71
Pregunta
37. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Respuesta
-
o Average time per task in the queue
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 72
Pregunta
36. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Respuesta
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 73
Pregunta
35. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Respuesta
-
o The time from the reception of the response until the user begins to enter the next command
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
Pregunta 74
Pregunta
34. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Respuesta
-
o The time between when the user enters the command and the complete response is displayed
-
o The time for the user to enter the command
-
o The time from the reception of the response until the user begins to enter the next command
Pregunta 75
Pregunta
33. What is kernel process?
Respuesta
-
o Provide at least two modes, indicating whether the running process is a user process or an operating system process
-
o Provide at least five modes, indicating whether the running process is a user process or an operating system process
-
o Provide a portion of the processor state that a user process can use but not write
-
o None of them
Pregunta 76
Pregunta
32. What does DDR stands for?
Respuesta
-
o Double data rate
-
o Dual data rate
-
o Double data reaction
-
o None of them
Pregunta 77
Pregunta
31. What does DRAM stands for?
Respuesta
-
o Dynamic Random Access memory
-
o Dual Random Access memory
-
o Dataram Random Access memory
Pregunta 78
Pregunta
30. What does SRAM stands for?
Respuesta
-
o Static Random Access memory
-
o System Random Access memory
-
o Short Random Accessmemory
-
o None of them
Pregunta 79
Pregunta
29. What is the cycle time?
Respuesta
-
o The minimum time between requests to memory.
-
o Time between when a read is requested and when the desired word arrives
-
o The maximum time between requests to memory.
-
o None of them
Pregunta 80
Pregunta
28. What is the access time?
Respuesta
-
o Time between when a read is requested and when the desired word arrives
-
o The minimum time between requests to memory.
-
o Describes the technology inside the memory chips and those innovative, internal organizations
-
o None of them
Pregunta 81
Pregunta
27. Data Hazard:
Respuesta
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 82
Pregunta
26. Structural Hazard:
Respuesta
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o An instruction depends on a data value produced by an earlier instruction
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 83
Pregunta
25. Exploit spatial locality:
Respuesta
-
o by fetching blocks of data around recently accessed locations
-
o by remembering the contents of recently accessed locations
-
o None of them
Pregunta 84
Pregunta
24. Exploit temporal locality:
Respuesta
-
o by remembering the contents of recently accessed locations
-
o None of them
-
o by fetching blocks of data around recently accessed locations
Pregunta 85
Pregunta
23. Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Respuesta
-
o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
o If cache size is doubled, miss rate usually drops by about √2
-
o None of them
Pregunta 86
Pregunta
22. Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Respuesta
-
o If cache size is doubled, miss rate usually drops by about √2
-
o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
o None of them
Pregunta 87
Pregunta
21. Cache Hit -
Respuesta
-
o Write Through – write both cache and memory, generally higher traffic but simpler to design
-
o write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
-
o No Write Allocate – only write to main memory
Pregunta 88
Pregunta
20. Least Recently Used (LRU):
Respuesta
-
o cache state must be updated on every access
-
o Used in highly associative caches
-
o FIFO with exception for most recently used block(s)
Pregunta 89
Pregunta
19. What is Computer Architecture?
Respuesta
-
o is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
-
o is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
-
o the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Pregunta 90
Pregunta
18. What is a Bandwidth-Delay Product:
Respuesta
-
o is amount of data that can be in flight at the same time (Little’s Law)
-
o is time for a single access – Main memory latency is usually >> than processor cycle time
-
o is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
Pregunta 91
Pregunta
17. What is a Bandwidth:
Respuesta
-
o a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
o is time for a single access – Main memory latency is usually >> than processor cycle time
-
o is amount of data that can be in flight at the same time (Little’s Law)
Pregunta 92
Pregunta
16. Control Hazard:
Respuesta
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Pregunta 93
Pregunta
15. Data Hazard:
Respuesta
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 94
Pregunta
1. Structural Hazard:
Respuesta
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o An instruction depends on a data value produced by an earlier instruction
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 95
Pregunta
13. The formula of “Iron Law” of Processor Performance:
Respuesta
-
o time/program = instruction/program * cycles/instruction * time/cycle
-
o time/program = instruction/program * cycles/instruction + time/cycle
-
o time/program = instruction/program + cycles/instruction * time/cycle
Pregunta 96
Pregunta
12. Algorithm for Cache MISS:
Respuesta
-
o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
-
o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
Pregunta 97
Pregunta
11. Algorithm for Cache HIT:
Respuesta
-
o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
-
o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
Pregunta 98
Pregunta
9. Capacity -
Respuesta
-
o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
-
o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
o first-reference to a block, occur even with infinite cache
Pregunta 99
Pregunta
8. Compulsory -
Respuesta
-
o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
-
o first-reference to a block, occur even with infinite cache
-
o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
Pregunta 100
Pregunta
7. Average Memory Access Time is equal:
Respuesta
-
o Hit Time * ( Miss Rate + Miss Penalty )
-
o Hit Time - ( Miss Rate + Miss Penalty )
-
o Hit Time / ( Miss Rate - Miss Penalty )
-
o Hit Time + ( Miss Rate * Miss Penalty )
Pregunta 101
Pregunta
6. Cache MISS:
Respuesta
-
o No Write Allocate, Write Allocate
-
o Write Through, Write Back
Pregunta 102
Pregunta
5. Cache HIT:
Respuesta
-
o No Write Allocate, Write Allocate
-
o Write Through, Write Back
Pregunta 103
Pregunta
4. What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Respuesta
-
o subroutine call
-
o n loop iterations
-
o vector access
Pregunta 104
Pregunta
3. What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Respuesta
-
o subroutine call
-
o n loop iterations
-
o vector access
Pregunta 105
Pregunta
2. What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Respuesta
-
o n loop iterations
-
o subroutine call
-
o vector access
Pregunta 106
Pregunta
1. - What is a Latency:
Respuesta
-
o is time for a single access – Main memory latency is usually >> than processor cycle time
-
o is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
o is amount of data that can be in flight at the same time (Little’s Law)
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