13867933
Descripción
Test por Alisher Kassymov , actualizado hace más de 1 año
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Creado por Alisher Kassymov
hace casi 6 años
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|
Pregunta 1
Pregunta
What is a Latency:
Respuesta
-
is amount of data that can be in flight at the same time (Little’s Law)
-
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
Pregunta 2
Pregunta
What occurs at Intruction fetches when we speak about Common And Predictable Memory
Reference Patterns?
Respuesta
-
n loop iterations
-
subroutine call
-
vector access
Pregunta 3
Pregunta
What occurs at Stack access when we speak about Common And Predictable Memory
Reference Patterns?
Respuesta
-
n loop iterations
-
subroutine call
-
vector access
Pregunta 4
Pregunta
What occurs at Data access when we speak about Common And Predictable Memory
Reference Patterns?
Respuesta
-
subroutine call
-
n loop iterations
-
vector access
Pregunta 5
Pregunta
Cache HIT:
Respuesta
-
No Write Allocate, Write Allocate
-
Write Through, Write Back
Pregunta 6
Pregunta
Cache MISS:
Respuesta
-
No Write Allocate, Write Allocate
-
Write Through, Write Back
Pregunta 7
Pregunta
Average Memory Access Time is equal:
Respuesta
-
Hit Time * ( Miss Rate + Miss Penalty )
-
Hit Time - ( Miss Rate + Miss Penalty )
-
Hit Time / ( Miss Rate - Miss Penalty )
-
Hit Time + ( Miss Rate * Miss Penalty )
Pregunta 8
Pregunta
Compulsory -
Respuesta
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
Pregunta 9
Pregunta
Capacity -
Respuesta
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
first-reference to a block, occur even with infinite cache
Pregunta 10
Pregunta
Conflict -
Respuesta
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
Pregunta 11
Pregunta
Algorithm for Cache HIT:
Respuesta
-
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
-
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
Pregunta 12
Pregunta
Algorithm for Cache MISS:
Respuesta
-
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
-
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
Pregunta 13
Pregunta
The formula of “Iron Law” of Processor Performance:
Respuesta
-
time/program = instruction/program * cycles/instruction * time/cycle
-
time/program = instruction/program * cycles/instruction + time/cycle
-
time/program = instruction/program + cycles/instruction * time/cycle
Pregunta 14
Pregunta
Structural Hazard:
Respuesta
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 15
Pregunta
Data Hazard:
Respuesta
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
An instruction depends on a data value produced by an earlier instruction
Pregunta 16
Pregunta
Control Hazard:
Respuesta
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Pregunta 17
Pregunta
What is a Bandwidth:
Respuesta
-
a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Pregunta 18
Pregunta
What is a Bandwidth-Delay Product:
Respuesta
-
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Pregunta 19
Pregunta
What is Computer Architecture?
Respuesta
-
the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
-
is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
-
is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
Pregunta 20
Pregunta
Least Recently Used (LRU):
Respuesta
-
FIFO with exception for most recently used block(s)
-
Used in highly associative caches
-
cache state must be updated on every access
Pregunta 21
Pregunta
Cache Hit -
Respuesta
-
Write Through – write both cache and memory, generally higher traffic but simpler to design
-
write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
-
No Write Allocate – only write to main memory
Pregunta 22
Pregunta
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Respuesta
-
None of them
-
If cache size is doubled, miss rate usually drops by about √2
-
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
Pregunta 23
Pregunta
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Respuesta
-
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
None of them
-
If cache size is doubled, miss rate usually drops by about √2
Pregunta 24
Pregunta
Exploit temporal locality:
Respuesta
-
by remembering the contents of recently accessed locations
-
by fetching blocks of data around recently accessed locations
-
None of them
Pregunta 25
Pregunta
Exploit spatial locality:
Respuesta
-
None of them
-
by remembering the contents of recently accessed locations
-
by fetching blocks of data around recently accessed locations
Pregunta 26
Pregunta
Structural Hazard:
Respuesta
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Pregunta 27
Pregunta
Data Hazard:
Respuesta
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction depends on a data value produced by an earlier instruction
Pregunta 28
Pregunta
What is the access time?
Respuesta
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
None of them
Pregunta 29
Pregunta
What is the cycle time?
Respuesta
-
The minimum time between requests to memory
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of them
Pregunta 30
Pregunta
What does SRAM stands for?
Respuesta
-
System Random Access memory
-
Static Random Access memory
-
Short Random Accessmemory
-
None of them
Pregunta 31
Pregunta
What does DRAM stands for?
Respuesta
-
Dataram Random Access memory
-
Dual Random Access memory
-
Dynamic Random Access memory
Pregunta 32
Pregunta
What does DDR stands for?
Respuesta
-
None of them
-
Double data reaction
-
Dual data rate
-
Double data rate
Pregunta 33
Pregunta
What is kernel process?
Respuesta
-
Provide at least two modes, indicating whether the running process is a user process or an operating system process
-
Provide a portion of the processor state that a user process can use but not write
-
Provide at least five modes, indicating whether the running process is a user process or an operating system process
-
None of them
Pregunta 34
Pregunta
Which one is NOT concerning to pitfall?
Respuesta
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
Predicting cache performance of one program from another
-
Over emphasizing memory bandwidth in DRAMs
Pregunta 35
Pregunta
Which one is concerning to fallacy?
Respuesta
-
Over emphasizing memory bandwidth in DRAMs
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
Predicting cache performance of one program from another
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
Pregunta 36
Pregunta
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “System response time” - ?:
Respuesta
-
The time from the reception of the response until the user begins to enter the next command
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
Pregunta 37
Pregunta
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Think time” - ?:
Respuesta
-
The time from the reception of the response until the user begins to enter the next command
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
Pregunta 38
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time
server” - :
Respuesta
-
Average time per task in the queue
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
Pregunta 39
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time
queue” - :
Respuesta
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
-
Average time per task in the queue
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 40
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time
system” - :
Respuesta
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
-
Average time per task in the queue
Pregunta 41
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :
Respuesta
-
Average length of queue
-
Average number of tasks in service
Pregunta 42
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:
Respuesta
-
Average length of queue
-
Average number of tasks in service
Pregunta 43
Pregunta
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Respuesta
-
4
-
3
-
2
-
1
Pregunta 44
Pregunta
How many issue queue used in Distributed Superscalar 2 and Exceptions:
Respuesta
-
4
-
3
-
1
-
2
Pregunta 45
Pregunta
How many instructions used in Distributed Superscalar 2 and Exceptions?
Respuesta
-
4
-
3
-
2
-
1
Pregunta 46
Pregunta
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Respuesta
-
1
-
2
-
3
-
4
Pregunta 47
Pregunta
Which of the following formula is true about Issue Queue for “Instruction Ready”:
Respuesta
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
-
Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
-
Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
Pregunta 48
Pregunta
What is a ARF:
Respuesta
-
Architectural Register File
-
Architecture Relocation File
-
Architecture Reload File
-
Architectural Read File
Pregunta 49
Pregunta
What is a ROB?
Respuesta
-
Read Only Buffer
-
Reorder Buffer
-
Reload Buffer
-
Recall Buffer
Pregunta 50
Pregunta
What is a FSB?
Respuesta
-
Finished Star Buffer
-
Finished Stall Buffer
-
Finished Store Buffer
-
Finished Stack Buffer
Pregunta 51
Pregunta
What is a PRF?
Respuesta
-
Pure Register File
-
Physical Register File
-
Pending Register File
-
Pipeline Register File
Pregunta 52
Pregunta
What is a SB?
Respuesta
-
Scalebit
-
Scaleboard
-
Scorebased
-
Scoreboard
Pregunta 53
Pregunta
How many stages used in Superscalar (Pipeline)?
Respuesta
-
5
-
4
-
6
-
7
Pregunta 54
Pregunta
What is about Superscalar means “F-D-X-M-W”?
Respuesta
-
Fetch, Decode, Instruct, Map, Write
-
Fetch, Decode, Execute, Memory, Writeback
-
Fetch, Decode, Excite, Memory, Write
-
Fetch, Decode, Except, Map, Writeback
Pregunta 55
Pregunta
Speculating on Exceptions “Prediction mechanism” is -
Respuesta
-
None of them
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
Pregunta 56
Pregunta
Speculating on Exceptions “Check prediction mechanism” is -
Respuesta
-
The way in which an object is accessed by a subject
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
None of them
Pregunta 57
Pregunta
Speculating on Exceptions “Recovery mechanism” is
Respuesta
-
None of them
-
An entity capable of accessing objects
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
Pregunta 58
Pregunta
What is a RT?
Respuesta
-
Rename Table
-
Recall Table
-
Relocate Table
-
Remove Table
Pregunta 59
Pregunta
What is a FL?
Respuesta
-
Free Launch
-
Free List
-
Free Leg
-
Free Last
Pregunta 60
Pregunta
What is an IQ?
Respuesta
-
Internal Queue
-
Instruction Queue
-
Issue Queue
-
Interrupt Queue
Pregunta 61
Pregunta
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Respuesta
-
Width and Height
-
Width and Lifetime
-
Time and Cycle
-
Length and Addition
Pregunta 62
Pregunta
Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?
Respuesta
-
Register name
-
Instruction cache
-
Data tags
-
Data cache
Pregunta 63
Pregunta
Out-of-Order Control Complexity MIPS R10000 which element is not in Control
Logic?
Respuesta
-
Integer Datapath
-
CLK
-
Address Queue
-
Free List
Pregunta 64
Pregunta
What is “VLIW”?
Respuesta
-
Very Less Interpreter Word
-
Very Long Instruction Word
-
Very Light Internal Word
-
Very Low Invalid Word
Pregunta 65
Pregunta
At VLIW by “performance and loop iteration” which time is longer?
Respuesta
-
Loop Unrolled
-
Software Pipelined
Pregunta 66
Pregunta
At VLIW by “performance and loop iteration” which time is shorter?
Respuesta
-
Loop Unrolled
-
Software Pipelined
Pregunta 67
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?
Respuesta
-
Hardware to check pointer hazards
-
Speculative operations that don’t cause exceptions
Pregunta 68
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem:
Possible memory hazards limit code scheduling:
Respuesta
-
Hardware to check pointer hazards
-
Speculative operations that don’t cause exceptions
Pregunta 69
Pregunta
What is an ALAT? :
Respuesta
-
Advanced Load Address Table
-
Allocated Link Address Table
-
Allowing List Address Table
-
Addition Long Accessibility Table
Pregunta 70
Pregunta
At VLIW Multi-Way Branches, which of this solution is true about problem: Long
instructions provide few opportunities for branches:
Respuesta
-
Allow one instruction to branch multiple directions
-
Speculative operations that don’t cause exceptions
Pregunta 71
Pregunta
What is a Compulsory?
Respuesta
-
first-reference to a block, occur even with infinite cache
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
misses that occur because of collisions due to less than full associativity
Pregunta 72
Pregunta
What is a Capacity?
Respuesta
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
misses that occur because of collisions due to less than full associativity
-
first-reference to a block, occur even with infinite cache
Pregunta 73
Pregunta
What is a Conflict?
Respuesta
-
misses that occur because of collisions due to less than full associativity
-
first-reference to a block, occur even with infinite cache
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
Pregunta 74
Pregunta
In Multilevel Caches “Local miss rate” equals =
Respuesta
-
misses in cache / accesses to cache
-
misses in cache / CPU memory accesses
-
misses in cache / number of instructions
Pregunta 75
Pregunta
In Multilevel Caches “Global miss rate” equals =
Respuesta
-
misses in cache / CPU memory accesses
-
misses in cache / accesses to cache
-
misses in cache / number of instructions
Pregunta 76
Pregunta
In Multilevel Caches “Misses per instruction” equals =
Respuesta
-
misses in cache / number of instructions
-
misses in cache / accesses to cache
-
misses in cache / CPU memory accesses
Pregunta 77
Pregunta
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
Respuesta
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Pregunta 78
Pregunta
Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Respuesta
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Pregunta 79
Pregunta
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
Respuesta
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
Pregunta 80
Pregunta
What does mean MSHR?
Respuesta
-
Miss Status Handling Register
-
Map Status Handling Reload
-
Mips Status Hardware Register
-
Memory Status Handling Register
Pregunta 81
Pregunta
What does MAF?
Respuesta
-
Miss Address File
-
Map Address File
-
Memory Address File
Pregunta 82
Pregunta
At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking
Cache “Order of fill”:
Respuesta
-
0,1,2,3,4,5,6,7
-
3,4,5,6,7,0,1,2
Pregunta 83
Pregunta
At Critical Word First for Miss Penalty chose correct sequence of Blocking
Cache with Critical Word first “Order of fill”:
Respuesta
-
3,4,5,6,7,0,1,2
-
0,1,2,3,4,5,6,7
Pregunta 84
Pregunta
Storage Systems, “Larger block size to reduce miss rate”
Respuesta
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Pregunta 85
Pregunta
Storage Systems, “Bigger caches to reduce miss rate” -
Respuesta
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Pregunta 86
Pregunta
Storage Systems, “Higher associativity to reduce miss rate” -
Respuesta
-
Obviously, increasing associativity reduces conflict misses
-
The obvious way to reduce capacity misses is to increase cache capacity
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Pregunta 87
Pregunta
In Non-Blocking Caches what does mean “Critical Word First”?
Respuesta
-
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
-
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
Pregunta 88
Pregunta
In Non-Blocking Caches what does mean “Early restart”?
Respuesta
-
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
-
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Pregunta 89
Pregunta
A virus classification by target includes the following categories, What is a File
infector?
Respuesta
-
A typical approach is as follows
-
Infects files that the operating system or shell consider to be executable
-
The key is stored with the virus
-
Far more sophisticated techniques are possible
Pregunta 90
Pregunta
What is a RAID 0?
Respuesta
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
-
This organization was inspired by applying memory-style error correcting codes to disks
Pregunta 91
Pregunta
What is a RAID 1?
Respuesta
-
Also called mirroring or shadowing, there are two copies of every piece of data
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
This organization was inspired by applying memory-style error correcting codes to disks
Pregunta 92
Pregunta
What is a RAID 2?
Respuesta
-
This organization was inspired by applying memory-style error correcting codes to disks
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 93
Pregunta
What is a RAID 3?
Respuesta
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
Many applications are dominated by small accesses
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 94
Pregunta
What is a RAID 4?
Respuesta
-
Many applications are dominated by small accesses
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 95
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean
“Hardware faults”? :
Respuesta
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
-
Mistakes by operations and maintenance personnel
Pregunta 96
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean “Design
faults”? :
Respuesta
-
Faults in software (usually) and hardware design (occasionally)
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Mistakes by operations and maintenance personnel
Pregunta 97
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean
“Operation faults”? :
Respuesta
-
Mistakes by operations and maintenance personnel
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
Pregunta 98
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean
“Environmental faults”? :
Respuesta
-
Fire, flood, earthquake, power failure, and sabotage
-
Faults in software (usually) and hardware design (occasionally)
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Pregunta 99
Pregunta
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Entry time” - ? :
Respuesta
-
The time for the user to enter the command
-
The time between when the user enters the command and the complete response is displayed
-
The time from the reception of the response until the user begins to enter the next command
Pregunta 100
Pregunta
If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “System response time” - ?:
Respuesta
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
-
The time from the reception of the response until the user begins to enter the next command
Pregunta 101
Pregunta
If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “Think time” - ?:
Respuesta
-
The time from the reception of the response until the user begins to enter the next command
-
The time for the user to enter the command
-
The time between when the user enters the command and the complete response is displayed
Pregunta 102
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Time server” - :
Respuesta
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time per task in the queue
Pregunta 103
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Time queue” - :
Respuesta
-
Average time per task in the queue
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 104
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Time system” - :
Respuesta
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
-
Average time per task in the queue
Pregunta 105
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :
Respuesta
-
Average number of tasks in service
-
Average length of queue
Pregunta 106
Pregunta
Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:
Respuesta
-
Average length of queue
-
Average number of tasks in service
Pregunta 107
Pregunta
How many size of Cache L1 is true approximately? :
Respuesta
-
8 KB
-
256 KB
-
2 MB
Pregunta 108
Pregunta
How many size of Cache L2 is true approximately?
Respuesta
-
256 KB
-
4 KB
-
32 MB
Pregunta 109
Pregunta
How many size of Cache L3 is true approximately?
Respuesta
-
3 MB
-
256 MB
-
256 KB
Pregunta 110
Pregunta
How many main levels of Cache Memory?
Respuesta
-
3
-
2
-
6
-
8
Pregunta 111
Pregunta
What is a “Synchronization” in Cache Memory?
Respuesta
-
Execution or waiting for synchronization variables
-
Execution in the OS that is neither idle nor in synchronization access
-
Execution in user code
Pregunta 112
Pregunta
What is a “Kernel” in Cache Memory?
Respuesta
-
Execution or waiting for synchronization variables
-
Execution in the OS that is neither idle nor in synchronization access
-
Execution in user code
Pregunta 113
Pregunta
What is a “Synchronization” in Cache Memory?
Respuesta
-
Execution in the OS that is neither idle nor in synchronization access
-
Execution in user code
-
Execution or waiting for synchronization variables
Pregunta 114
Pregunta
Network performance depends of what?
Respuesta
-
performance of swithes and transmission system
-
performance of switches
-
performance of transmission system
-
has no dependensies
Pregunta 115
Pregunta
The time between the start and the completion of an event ,such as milliseconds
for a disk access is...
Respuesta
-
latency
-
bandwidth
-
throughput
-
performance
Pregunta 116
Pregunta
Total amount of work done in a given time ,such as megabytes per second for disk
transfer...
Respuesta
-
bandwidth
-
latency
-
throughput
-
performance
Pregunta 117
Pregunta
Learning curve itself is best measured by change in...
Respuesta
-
yeld
-
bytes
-
bits
-
seconds
Pregunta 118
Pregunta
Products that are sold by multiple vendors in large volumes and are essentialy
identical
Respuesta
-
commodities
-
boxes
-
folders
-
files
Pregunta 119
Pregunta
Integrated circuit processes are charecterized by the
Respuesta
-
feature size
-
permanent size n
-
compex size
-
fixed size
Pregunta 120
Pregunta
For CMOS chips, the traditional dominant energy consumption has been in
switching transistors, called ____
Respuesta
-
dynamic power
-
physical energy
-
constant supply
-
simple battery
Pregunta 121
Pregunta
Manufacturing costs that decrease over time are ____
Respuesta
-
the learning curve
-
the cycled line
-
the regular option
-
the final loop
Pregunta 122
Pregunta
Volume is a ________ key factor in determining cost
Respuesta
-
second
-
first
-
fifth
-
third
Pregunta 123
Pregunta
The most companies spend only ____________ of their income on R&D, which
includes all engineering.
Respuesta
-
4% to 12%
-
15% to 30%
-
1% to 17%
-
30% to 48%
Pregunta 124
Pregunta
Systems alternate between two states of service with respect to an SLA:
Respuesta
-
1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
-
1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
-
1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
-
1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
Pregunta 125
Pregunta
Desktop benchmarks divide into __ broad classes:
Respuesta
-
two
-
three
-
four
-
five
Pregunta 126
Pregunta
What MTTF means:
Respuesta
-
mean time to failure
-
mean time to feauture
-
mean this to failure
-
my transfers to failure
Pregunta 127
Pregunta
A widely held rule of thumb is that a program spends __ of its execution time in
only __ of the code.
Respuesta
-
90% 10%
-
50% 50%
-
70% 30%
-
89% 11%
Pregunta 128
Pregunta
(Performance for entire task using the enhancement when possible) / (Performance
for entire task without using the enhancement) is equals to:
Respuesta
-
Speedup
-
Efficiency
-
Probability
-
Ration
Pregunta 129
Pregunta
Which of the following descriptions corresponds to static power?
Respuesta
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Proportional to the product of the number of switching transistors and the switching rate Probability
-
Proportional to the product of the number of switching transistors and the switching rate
-
All of the above
Pregunta 130
Pregunta
Which of the following descriptions corresponds to dynamic power?
Respuesta
-
Proportional to the product of the number of switching transistors and the switching rate
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Certainly a design concern
-
None of the above
Pregunta 131
Pregunta
Which of the written below is NOT increase power consumption?
Respuesta
-
Increasing multithreading
-
Increasing performance
-
Increasing multiple cores
-
Increasing multithreading (V baze tak napisano)
Pregunta 132
Pregunta
Growing performance gap between peak and sustained performance translates to
increasing energy per unit of performance, when:
Respuesta
-
The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
-
The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
-
The number of transistors switching will be proportional to the sustained rate
-
The performance is proportional to the peak issue rate
Pregunta 133
Pregunta
If we want to sustain four instructions per clock
Respuesta
-
We must fetch more, issue more, and initiate execution on more than four instructions
-
We must fetch less, issue more, and initiate execution on more than two instructions
-
We must fetch more, issue less, and initiate execution on more than three instructions
-
We must fetch more, issue more, and initiate execution on less than five instructions
Pregunta 134
Pregunta
If speculation were perfect, it could save power, since it would reduce the execution time and
save _____________, while adding some additional overhead to implement
Respuesta
-
Static power
-
Dynamic power
-
Processing rate
-
Processor state
Pregunta 135
Pregunta
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires
additional ___________ both for the incorrect speculation and for the resetting of the processor
state
Respuesta
-
Dynamic power
-
Static power
-
Processing rate
-
Processor state
Pregunta 136
Pregunta
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W.
Sias
Respuesta
-
Achievable ILP with software resource constraints
-
Limited ILP due to software dependences
-
Achievable ILP with hardware resource constraints
-
Variability of ILP due to software and hardware interaction
Pregunta 137
Pregunta
What is a hash table?
Respuesta
-
Popular data structure for organizing a large collection of data items so that one can quickly answer questions
-
Popular data structure for updating large collections, so that one can hardly answer questions
-
Popular tables for organizing a large collection of data structure
-
Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
Pregunta 138
Pregunta
Which of these is NOT characteristics of recent highperformance microprocessors?
Respuesta
-
Color
-
Power
-
Functional unit capability
-
Clock rate
Pregunta 139
Pregunta
How this process called: “Operations execute as soon as their operands are available”
Respuesta
-
data flow execution
-
instruction execution
-
data control execution
-
instruction field execution
Pregunta 140
Pregunta
For what the reorder buffer is used :
Respuesta
-
To pass results among instructions that may be speculated
-
To pass parameters through instructions that may be speculated
-
To get additional registers in the same way as the reservation stations
-
To control registers
Pregunta 141
Pregunta
How many fields contains the entry in the ROB:
Respuesta
-
4
-
5
-
6
-
3
Pregunta 142
Pregunta
Choose correct fields of entry in the ROB:
Respuesta
-
the instruction type, the destination field, the value field, and the ready field
-
the source type, the destination field, the value field, and the ready field
-
the program type, the ready field, the parameter field, the destination field
-
the instruction type, the destination field, and the ready field
Pregunta 143
Pregunta
Choose the steps of instruction execution:
Respuesta
-
issue, execute, write result, commit
-
execution, commit, rollback
-
issue, execute, override, exit
-
begin, write, interrupt, commit
Pregunta 144
Pregunta
Which one is not the major flavor of Multiple-issue processors
Respuesta
-
statistically superscalar processors
-
dynamically scheduled superscalar processors
-
statically scheduled superscalar processors
-
VLIW (very long instruction word) processors
Pregunta 145
Pregunta
Which Multiple-issue processors has not the hardware hazard detection
Respuesta
-
EPIC
-
Superscalar(dynamic)
-
Superscalar(static)
-
Superscalar(speculative)
Pregunta 146
Pregunta
Examples of EPIC:
Respuesta
-
Itanium
-
Pentium 4, MIPS R12K, IBM, Power5
-
MIPS and ARM
-
TI C6x
Pregunta 147
Pregunta
Examples of superscalar(static):
Respuesta
-
MIPS and ARM
-
Pentium 4, MIPS R12K, IBM, Power5
-
Itanium
-
TI C6x
Pregunta 148
Pregunta
Examples of superscalar(dynamic) :
Respuesta
-
None at the present
-
Pentium 4, MIPS R12K, IBM, Power5
-
MIPS and ARM
-
TI C6x
Pregunta 149
Pregunta
Examples of VLIW/LIW:
Respuesta
-
TI C6x
-
MIPS and ARM
-
Itanium
-
Pentium 4, MIPS R12K, IBM, Power5
Pregunta 150
Pregunta
A branch-prediction cache that stores the predicted address for the next instruction after a
branch
Respuesta
-
branch-target buffer
-
data buffer
-
frame buffer
-
optical buffer
Pregunta 151
Pregunta
Buffering the actual target instructions allows us to perform an optimization which called:
Respuesta
-
branch folding
-
Branch prediction
-
Target instructions
-
Target address
Pregunta 152
Pregunta
Which is not the function of integrated instruction fetch unit:
Respuesta
-
Instruction memory commit
-
Integrated branch prediction
-
Instruction prefetch
-
Instruction memory access and buffering
Pregunta 153
Pregunta
What is the simple technique that predicts whether two stores or a load and a store refer to
the same memory address:
Respuesta
-
Address aliasing prediction
-
Branch prediction
-
Integrated branch prediction
-
Dynamic branch prediction
Pregunta 154
Pregunta
How to decrypt RISC?
Respuesta
-
Reduced Instruction Set Computer
-
Recall Instruction Sell Communication
-
Rename Instruction Sequence Corporation
-
Red Instruction Small Computer
Pregunta 155
Pregunta
The ideal pipeline CPI is a measure of …
Respuesta
-
the maximum performance attainable by the implementation
-
the maximum performance attainable by the instruction
-
the minimum performance attainable by the implementation
-
the minimum performance attainable by the instruction
Pregunta 156
Pregunta
What is the Pipeline CP = ?
Respuesta
-
deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
-
deal pipeline CPU + Data hazard stalls + Control stalls
-
deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
-
Structural stalls + Data hazard stalls + Control stalls
Pregunta 157
Pregunta
The simplest and most common way to increase the ILP is …?
Respuesta
-
to exploit parallelism among iterations of a loop
-
to exploit minimalism among iterations of a loop
-
to destroy iterations of a loop
-
to decrease the minimalism of risk
Pregunta 158
Pregunta
The simplest and most common way to increase the ILP is to exploit parallelism among
iterations of a loop. How is often called?
Respuesta
-
loop-level parallelism
-
exploit-level parallelism
-
high-level minimalism
-
low-level minimalism
Pregunta 159
Pregunta
In parallelism have three different types of dependences, tagging him:
Respuesta
-
data dependences , name dependences , and control dependences
-
data dependences , name dependences , and surname dependences
-
datagram dependences , name dependences , and animal dependences
-
no correct answers
Pregunta 160
Pregunta
What is Name dependence?
Respuesta
-
name dependence occurs when two instructions use the same register or memory location
-
name dependence occurs when five or more instructions use the same register or memory location
-
name dependence occurs when instructions use the same name
-
All answers is correct
Pregunta 161
Pregunta
When occurs an output dependence?
Respuesta
-
When i and instruction j write the same register or memory location
-
when i and instruction j write the same name
-
when i and instruction j write the same adress or memory location
-
All answers is correct
Pregunta 162
Pregunta
What is RAW (read after write)?
Respuesta
-
when j tries to read a source before i writes it, so j incorrectly gets the old value
-
when i tries to read a source before j writes it, so j correctly gets the old value
-
when j tries to write a source before i writes it
-
when a tries to write a source before b read it, so a incorrectly gets the old value
Pregunta 163
Pregunta
What is given is not a hazard?
Respuesta
-
RAR
-
WAR
-
WAW
-
LOL
Pregunta 164
Pregunta
A simple scheme for increasing the number of instructions relative to the branch and
overhead instructions is…?
Respuesta
-
loop unrolling
-
RAR
-
loop-level
-
loop rolling
Pregunta 165
Pregunta
Effect that results from instruction scheduling in large code segments is called…?
Respuesta
-
register pressure
-
loop unrolling
-
loop-level
-
registration
Pregunta 166
Pregunta
The simplest dynamic branch-prediction scheme is a
Respuesta
-
branch-prediction buffer
-
branch buffer
-
All answers correct
-
registration
Pregunta 167
Pregunta
Branch predictors that use the behavior of other branches to make a prediction are called
Respuesta
-
correlating predictors or two-level predictors
-
branch-prediction buffer
-
branch table
-
three level loop
Pregunta 168
Pregunta
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the
prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Respuesta
-
the number of prediction entries selected by the branch = 1K.
-
the number of prediction entries selected by the branch = 2K.
-
the number of prediction entries selected by the branch = 8K.
-
the number of prediction entries selected by the branch = 4K.
Pregunta 169
Pregunta
What is the compulsory in Cs model?
Respuesta
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Pregunta 170
Pregunta
What is capacityin Cs model?
Respuesta
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Pregunta 171
Pregunta
What is conflict in Cs model?
Respuesta
-
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
None of them
Pregunta 172
Pregunta
Choose the benefit of Cache Optimization.
Respuesta
-
Larger block size to reduce miss rate
-
Bigger caches to increase miss rat
-
Single level caches to reduce miss penalty
-
None of them
Pregunta 173
Pregunta
Choose the strategy of Seventh Optimization.
Respuesta
-
Critical word first
-
Critical restart
-
Sequential inter leaving
-
Merging Write Buffer to Reduce Miss Penalty
Pregunta 174
Pregunta
Choose the Eight Optimization
Respuesta
-
Merging Write Buffer to Reduce Miss Penalty
-
Critical word first
-
Nonblocking Caches to Increase Cache Bandwidth
-
Trace Caches to Reduce Hit Time
Pregunta 175
Pregunta
Choose the Eleventh Optimization
Respuesta
-
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
-
Merging Write Buffer to Reduce Miss Penalty
-
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
-
None of them
Pregunta 176
Pregunta
What is the access time?
Respuesta
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
None of them
Pregunta 177
Pregunta
What is the cycle time?
Respuesta
-
The minimum time between requests to memory
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of them
Pregunta 178
Pregunta
How much in percentage single-processor performance improvement has dropped to
less than?
Respuesta
-
11%
-
22%
-
33%
Pregunta 179
Pregunta
How many elements of the Instruction Set Architecture (ISA):
Respuesta
-
6
-
7
-
8
Pregunta 180
Pregunta
What is the Thread Level Parallelism –
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Pregunta 181
Pregunta
What is the PMD in computer classes?
Respuesta
-
Personal mobile device
-
Powerful markup distance
-
Percentage map device
Pregunta 182
Pregunta
What is the Instruction Level Parallelism:
Respuesta
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Pregunta 183
Pregunta
How many elements in Trends of Technology?
Respuesta
-
5
-
6
-
4
Pregunta 184
Pregunta
What is the Vector Architecture and Graphic Processor Units (GPUs) –
Respuesta
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Pregunta 185
Pregunta
How many Optimizations’ in Cache memory Performance?
Respuesta
-
8
-
6
-
10
Pregunta 186
Pregunta
What is the Reducing the Miss Rate?
Respuesta
-
Time Optimization
-
Compiler Optimization
-
Performance Optimization
Pregunta 187
Pregunta
What is the Spatial Locality?
Respuesta
-
Exploit by fetching blocks of data around recently accessed locations
-
Exploit by remembering the contents of recently accessed locations
Pregunta 188
Pregunta
What is the Temporal Locality?
Respuesta
-
Exploit by fetching blocks of data around recently accessed locations
-
Exploit by remembering the contents of recently accessed locations
Pregunta 189
Pregunta
True formula of Module availability (MTTF – mean time to failure, MTTR – mean
time to repair)?
Respuesta
-
MTTF / (MTTF + MTTR)
-
MTTF * (MTTF + MTTR)
-
MTTF * (MTTF - MTTR)
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