13903216
Descripción
Test por Good Guy Beket, actualizado hace más de 1 año
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Creado por Good Guy Beket
hace casi 6 años
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Pregunta 1
Pregunta
Storage Systems, “Higher associativity to reduce miss rate”
Respuesta
-
The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Pregunta 2
Pregunta
How many Optimizations’ in Cache memory Performance?
Respuesta
-
6
-
8
-
10
Pregunta 3
Pregunta
Storage Systems, “Larger block size to reduce miss rate”
Respuesta
-
The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Pregunta 4
Pregunta
What is the “Read Operands” in simple five-stage pipeline?
Respuesta
-
Wait until no data hazards, then reads the operand
-
Decode instructions, check for structural hazards
Pregunta 5
Pregunta
Storage Systems, “Bigger caches to reduce miss rate”
Respuesta
-
The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Pregunta 6
Pregunta
Tenth optimization of Cache Memory “Register prefetch”?
Respuesta
-
Loads data only into the cache and not the register
-
Will load the value into register
Pregunta 7
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”?
Respuesta
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
-
Mistakes by operations and maintenance personnel
Pregunta 8
Pregunta
What is a “Kernel” in Cache Memory?
Respuesta
-
Execution or waiting for synchronization variables
-
Execution in user code
-
Execution in the OS that is neither idle nor in synchronization access
Pregunta 9
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Respuesta
-
Average time per task in the queue
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 10
Pregunta
How many steps took Virtual Machine Monitor to improve performance of virtual machines?
Respuesta
-
5
-
3
-
4
Pregunta 11
Pregunta
How many issue queue used in Centralized Superscalar 2 and Exceptions
Respuesta
-
4
-
3
-
2
-
1
Pregunta 12
Pregunta
Which of the following formula is true about Issue Queue for “Instruction Ready”
Respuesta
-
Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
-
Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
Pregunta 13
Pregunta
What is the “Read Operands” in Pipelining Basics?
Respuesta
-
Wait until no control hazards, then reads the operand
-
Wait until no structural hazards, then reads the operand
-
Wait until no data hazards, then reads the operand
Pregunta 14
Pregunta
Perfect caches at The Hardware Model?
Respuesta
-
All memory accesses take one clock cycle
-
All conditional branches are predicted exactly
-
All memory addresses are known exactly
Pregunta 15
Pregunta
How many stages used in Superscalar (Pipeline)?
Respuesta
-
4
-
5
-
6
-
7
Pregunta 16
Pregunta
How much in percentage single-processor performance improvement has dropped to less than?
Respuesta
-
22%
-
33%
-
11%
Pregunta 17
Pregunta
What is “VLIW”?
Respuesta
-
Very Long Instruction Word
-
Very Less Interpreter Word
-
Very Light Internal Word
-
Very Low Invalid Word
Pregunta 18
Pregunta
At VLIW by “performance and loop iteration” which time is shorter?
Respuesta
-
Software Pipelined
-
Loop Unrolled
Pregunta 19
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Respuesta
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
Average time per task in the queue
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Pregunta 20
Pregunta
What single-processor performance improvement has dropped?
Respuesta
-
2004
-
2002
-
2003
Pregunta 21
Pregunta
What does MAF?
Respuesta
-
Miss Address File
-
Map Address File
-
Memory Address File
Pregunta 22
Pregunta
How many classes of computers classified?
Respuesta
-
3
-
5
-
7
Pregunta 23
Pregunta
Sixth Optimization of Cache Memory “Critical word first”?
Respuesta
-
Fetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
-
Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block
Pregunta 24
Pregunta
In an important early study of intrusion, Anderson[ANDE80] identified three classes of intruders:
Respuesta
-
Control, exploit, system
-
Masquerader, misfeasor, clandestine user
-
Individual, legitimate, authorized
-
Outside, inside, offside
Pregunta 25
Pregunta
How many elements of the Instruction Set Architecture (ISA):
Respuesta
-
7
-
8
Pregunta 26
Pregunta
What is the “Bigger caches to reduce miss rate” at Basics of Memory Hierarchies
Respuesta
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Pregunta 27
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean “Design faults”?
Respuesta
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
-
Mistakes by operations and maintenance personnel
Pregunta 28
Pregunta
What is the ARF?
Respuesta
-
Architectural Register File
-
Architecture Relocation File
-
Architecture Reload File
-
Architectural Read File
Pregunta 29
Pregunta
What is the Conflict in main categories in Cache Memory?
Respuesta
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
Pregunta 30
Pregunta
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is?
Respuesta
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
Pregunta 31
Pregunta
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Respuesta
-
Width and Lifetime
-
Width and Height
-
Time and Cycle
-
Length and Addition
Pregunta 32
Pregunta
What is a “Synchronization” in Cache Memory?
Respuesta
-
Execution in the OS that is neither idle nor in synchronization access
-
Execution in user code
-
Execution or waiting for synchronization variables
Pregunta 33
Pregunta
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is?
Respuesta
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Pregunta 34
Pregunta
Flash memory is a type of?
Respuesta
-
Electronically Erasable Programmable Read-Only Memory
-
Electronically Extensible Programmable Re-Order Memory
-
Electronically Executable Programmable Reduce Memory
Pregunta 35
Pregunta
Access time at memory latency is -
Respuesta
-
The time between when a read is requested and when the desired word arrives
-
The minimum time between unrelated requests to memory
Pregunta 36
Pregunta
In Multilevel Caches “Local miss rate” equals =
Respuesta
-
misses in cache / accesses to cache
-
misses in cache / CPU memory accesses
-
misses in cache / number of instructions
Pregunta 37
Pregunta
What is a RAID 1?
Respuesta
-
Also called mirroring or shadowing, there are two copies of every piece of data
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
This organization was inspired by applying memory-style error correcting codes to disks
Pregunta 38
Pregunta
RAW (read after write)?
Respuesta
-
This hazard corresponds to an output dependence
-
This hazard is the most common type and corresponds to a true data dependence
-
This hazard arises n antidependence (or name dependence)
Pregunta 39
Pregunta
How many size of Cache L3 is true approximately?
Respuesta
-
3 MB
-
256 MB
-
256 KB
Pregunta 40
Pregunta
What is a RAID 3?
Respuesta
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
Many applications are dominated by small accesses
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 41
Pregunta
What is the increasing cache bandwidth?
Respuesta
-
Critical word first and merging write buffer
-
Pipelined caches, multibanked caches and non-blocking caches
-
Small and simple first-level caches and way-prediction
Pregunta 42
Pregunta
What is RAID 2?
Respuesta
-
This organization was inspired by applying memory-style error correcting codes to disks
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 43
Pregunta
In Non-Blocking Caches what does mean “Critical word first”?
Respuesta
-
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
-
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
Pregunta 44
Pregunta
Sixth optimization of cache memory “Early restart”?
Respuesta
-
Fetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
-
Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block
Pregunta 45
Pregunta
How many size of Cache L2 is true approximately?
Respuesta
-
256 KB
-
4 KB
-
32 MB
Pregunta 46
Pregunta
Reducing the miss penalty or miss rate via parallelism?
Respuesta
-
Hardware prefetching and compiler prefetching
-
Compiler optimization
-
Pipelined caches, multibanked caches and non-blocking caches
Pregunta 47
Pregunta
What is a RT?
Respuesta
-
Rename Table
-
Recall Table
-
Relocate Table
-
Remove Table
Pregunta 48
Pregunta
How many functions at integrated instruction fetch units?
Respuesta
-
3
-
4
-
5
Pregunta 49
Pregunta
What is the PMD in computer classes?
Respuesta
-
Percentage map device
-
Personal mobile device
-
Powerful markup distance
-
Peak maze development
Pregunta 50
Pregunta
The second type of dependence is?
Respuesta
-
Data dependence
-
Name dependence
-
Control dependence
Pregunta 51
Pregunta
How many elements presented at performance trends: bandwidth over latency?
Respuesta
-
4
-
5
-
3
Pregunta 52
Pregunta
What is the compulsory in main categories in cache memory?
Respuesta
-
Cache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)
-
Misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
First-reference to a block, occurs even with infinite cache
Pregunta 53
Pregunta
How many elements in trends of technology?
Respuesta
-
5
-
4
-
6
Pregunta 54
Pregunta
Perfect memory address alias analysis at the Hardware model?
Respuesta
-
All conditional branches are predicted exactly
-
All memory accesses take one clock cycle
-
All memory addresses are known exactly
Pregunta 55
Pregunta
Speculating on exceptions “Recovery mechanism” is –
Respuesta
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
None of them
-
An entity capable of accessing objects
Pregunta 56
Pregunta
What is the reducing the miss rate?
Respuesta
-
What is the reducing the miss rate?
-
Performance optimization
-
Compiler optimization
-
Time optimization
Pregunta 57
Pregunta
DDR is –
Respuesta
-
Double data rate
-
Density data rate
-
Dynamic data rate
Pregunta 58
Pregunta
In Non-blocking caches what does mean “Early restart”?
Respuesta
-
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
-
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Pregunta 59
Pregunta
Which distance of price has clusters/warehouse-scale computers?
Respuesta
-
100-100 000$
-
100 000-200 000 000$
-
5 000 -10 000 000$
Pregunta 60
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Time System”-
Respuesta
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
Average time per task in the queue
Pregunta 61
Pregunta
What is the MISD one of the categories of computers?
Respuesta
-
Multiple instructions streams, set data stream
-
Multiple instructions streams, single data stream
-
Multiple instruction stream, multiple data streams
Pregunta 62
Pregunta
What is a RAID 4?
Respuesta
-
Many applications are dominated by small accesses
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 63
Pregunta
Tenth Optimization of cache memory “Cache prefetch”?
Respuesta
-
Will load the value into a register
-
Loads data only into the cache and not the register
Pregunta 64
Pregunta
What is the Request level parallelism?
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or the operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Pregunta 65
Pregunta
Non-blocking cache timeline for “Hit under miss” the sequence is -?
Respuesta
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Pregunta 66
Pregunta
At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”?
Respuesta
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
-
Mistakes by operations and maintenance personnel
Pregunta 67
Pregunta
WAR(write after read)?
Respuesta
-
This hazard correspond to an output dependence
-
This hazard arises from an antidependence (or name dependence)
Pregunta 68
Pregunta
Main term of dependability is SLAs?
Respuesta
-
Scale level approach
-
Service level agreements
-
Standard level achievement
Pregunta 69
Pregunta
At VLIW by “performance and loop iteration” which time is longer?
Respuesta
-
Loop unrolled
-
Software Pipelined
Pregunta 70
Pregunta
What is the temporal locality?
Respuesta
-
Exploit by remembering the contents of recently accessed locations
-
Exploit by fetching blocks of data around recently accessed locations
Pregunta 71
Pregunta
What is an IQ?
Respuesta
-
Issue Queue
-
Internal Queue
-
Interrupt Queue
-
Instruction Queue
Pregunta 72
Pregunta
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time”-?
Respuesta
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
-
The time from the reception of the response until the user begins to enter the next command
Pregunta 73
Pregunta
How many size of Cache L1 is true approximately?
Respuesta
-
8 KB
-
256 KB
-
2 MB
Pregunta 74
Pregunta
What is a RISC computers?
Respuesta
-
Reduced instruction set computer
-
Research interconnect several computer
-
Rational interruptible security computer
Pregunta 75
Pregunta
The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
Respuesta
-
4
-
6
-
5
Pregunta 76
Pregunta
What is the “opcode”?
Respuesta
-
Operand code
-
Optional code
-
Operation code
Pregunta 77
Pregunta
WAW(write after write)?
Respuesta
-
This hazard arises from an antidependence (or name dependence)
-
This hazard corresponds to an output dependence
-
This hazard is the most common type and corresponds to a true data dependence
Pregunta 78
Pregunta
What is the Vector Architectures and graphic processor units(GPUs)?
Respuesta
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
Pregunta 79
Pregunta
Speculating on exceptions “Check prediction mechanism” is –
Respuesta
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
The way in which an object is accessed by a subject
-
None of them
Pregunta 80
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Respuesta
-
Speculative operations that don’t cause exceptions
-
Hardware to check pointer hazards
Pregunta 81
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:
Respuesta
-
Speculative operations that don’t cause exceptions
-
Hardware to check pointer hazards
Pregunta 82
Pregunta
What is PRF?
Respuesta
-
Pipeline Register File
-
Physical Register File
-
Pure Register File
-
Pending Register File
Pregunta 83
Pregunta
Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?
Respuesta
-
3
-
4
-
2
Pregunta 84
Pregunta
How many instructions used in Distributed Superscalar 2 and Exceptions?
Respuesta
-
1
-
2
-
3
-
4
Pregunta 85
Pregunta
What is about Superscalar means “F-D-X-M-W”?
Respuesta
-
Fetch, Decode, Instruct, Map, Write
-
Fetch, Decode, Excite, Memory, Write
-
Fetch, Decode, Except, Map, Writeback
-
Fetch, Decode, Execute, Memory, Writeback
Pregunta 86
Pregunta
SDRAM is -
Respuesta
-
Synchronous dynamic random access memory
-
Static dynamic random access memory
-
Super dynamic random access memory
Pregunta 87
Pregunta
How many restrictions RAW hazards through memory are maintained?
Respuesta
-
3
-
4
-
2
Pregunta 88
Pregunta
In Multilevel Caches “Misses per instruction” equals =
Respuesta
-
Misses in cache / number of instructions
-
Misses in cache / accesses to cache
-
Misses in cache / CPU memory accesses
Pregunta 89
Pregunta
How many possible Elements of Data Hazards?
Respuesta
-
3
-
6
-
8
Pregunta 90
Pregunta
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” ?
Respuesta
-
The time from the reception of the response until the user begins to enter the next command
-
The time for the user to enter the command
-
The time between when the user enters the command and the complete response is displayed
Pregunta 91
Pregunta
Clock cycle time is -
Respuesta
-
Hardware technology and organization
-
Organization and instruction set architecture
-
Instruction set architecture and compiler technology
Pregunta 92
Pregunta
A virus classification by target includes the following categories. What is a File infector?
Respuesta
-
The key is stored with the virus
-
Far more sophisticated techniques are possible
-
A typical approach is as follows
-
Infects files that the operating system or shell consider to be executable
Pregunta 93
Pregunta
What is an ALAT?
Respuesta
-
Addition Long Accessibility Table
-
Allocated Link Address Table
-
Allowing List Address Table
-
Advanced Load Address Table
Pregunta 94
Pregunta
CPI is -
Respuesta
-
Hardware technology and organization
-
Organization and instruction set architecture
-
Instruction set architecture and compiler technology
Pregunta 95
Pregunta
What is SB?
Respuesta
-
Scaleboard
-
Scoreboard
-
Scorebased
-
Scalebit
Pregunta 96
Pregunta
At Critical Word First for miss penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
Respuesta
-
0,1,2,3,4,5,6,7
-
3,4,5,6,7,0,1,2
Pregunta 97
Pregunta
At Critical Word First for miss penalty chose correct sequence of Blocking Cache with critical word first “Order of fill”:
Respuesta
-
0,1,2,3,4,5,6,7
-
3,4,5,6,7,0,1,2
Pregunta 98
Pregunta
What is a RAID 0?
Respuesta
-
This organization was inspired by applying memory-style errorcorrecting codes to disks
-
it has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
Pregunta 99
Pregunta
What is a file?
Respuesta
-
It is the basic element of data
-
it is a collection of related fields that can be treated as a unit by some application program
-
it is a collection of related data
-
it is a collection of similar records
Pregunta 100
Pregunta
What is the reducing the miss penalty?
Respuesta
-
Pipelined caches, multibanked caches, and nonblocking caches
-
Critical word first and merging write buffer
-
Small and simple first-level caches and way-prediction
Pregunta 101
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “length server”-:
Respuesta
-
Average length of queue
-
Average number of tasks in service
Pregunta 102
Pregunta
At storage systems gray and Siewiorek classify faults what does mean “environmental faults”?
Respuesta
-
Fire, flood, earthquake, power failure and sabotage
-
Faults in software (usually) and hardware design (occasionally)
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Pregunta 103
Pregunta
How many types of dependencies do you know?
Respuesta
-
3
-
4
-
5
Pregunta 104
Pregunta
How many major flavors in multiple-issue processors?
Respuesta
-
3
-
4
-
5
Pregunta 105
Pregunta
Out-of-order control complexity MIPS R10000 which is not in control logic?
Respuesta
-
CLK
-
Address queue
-
Integer datapath
-
Free list
Pregunta 106
Pregunta
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches
Respuesta
-
Allow one instruction to branch multiple directions
-
Speculative operations that don’t cause exceptions
Pregunta 107
Pregunta
Infinite register renaming at the hardware model?
Respuesta
-
There are an infinite number of virtual registers available
-
Branch prediction is perfect, all conditional branches are predicted exactly
Pregunta 108
Pregunta
What is reducing hit time?
Respuesta
-
Pipelined caches, multibanked caches, and nonblocking caches
-
Critical word first and merging write buffer
-
Small and simple first-level caches and way-prediction
Pregunta 109
Pregunta
Cycle time at memory latency is -
Respuesta
-
The time between when a read is requested and when the desired word arrives
-
the minimum time between unrelated requests to memory
Pregunta 110
Pregunta
Speculating on Exceptions “Prediction mechanism” is
Respuesta
-
None of them
-
exceptions are rare, so simply predicting no exceptions is very accurate
-
only write architecture state at commit point, so can throw away partially executed instructions after exception
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
Pregunta 111
Pregunta
How many main levels of cache memory?
Respuesta
-
2
-
8
-
3
-
6
Pregunta 112
Pregunta
What is the thread level parallelism -
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Pregunta 113
Pregunta
How many steps in instruction execution?
Respuesta
-
4
-
6
-
3
-
5
Pregunta 114
Pregunta
How many issue queue used in Centralized Superscalar 2 and exceptions?
Respuesta
-
2
-
4
-
3
-
1
Pregunta 115
Pregunta
What is a FL?
Respuesta
-
free leg
-
free list
-
free last
-
free launch
Pregunta 116
Pregunta
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time”-?
Respuesta
-
The time from the reception of the response until the user begins to enter the next command
-
the time between when the user enters the command and the complete response is displayed
-
the time for the user to enter the command
Pregunta 117
Pregunta
What is the “issue” in pipelining basics?
Respuesta
-
Decode instructions, check for data hazard
-
Decode instructions, check for control hazard
-
Decode instructions, check for structural hazard
Pregunta 118
Pregunta
Little’s Law and a series of definitions lead to several useful equations for “Length queue”
Respuesta
-
Average length of queue
-
Average number of tasks in service
Pregunta 119
Pregunta
Perfect jump prediction at The Hardware Model?
Respuesta
-
All jumps are perfectly predicted
-
All memory addresses are known exactly
-
Branch prediction is perfect
Pregunta 120
Pregunta
What is the term of dependability in SLOs?
Respuesta
-
Standard Level Offset
-
Standard Level Objectives
Pregunta 121
Pregunta
What is a FSB?
Respuesta
-
Finished store Buffer
-
Finished stack Buffer
-
Finished star Buffer
-
Finished stall Buffer
Pregunta 122
Pregunta
Out-of-order control complexity MIPS R10000 which is in control logic?
Respuesta
-
Data tags
-
Register name
-
Instruction cache
-
Data cache
Pregunta 123
Pregunta
Instruction count is –
Respuesta
-
Organization and instruction set architecture
-
Hardware technology and organization
-
Instruction set architecture and compiler technology
Pregunta 124
Pregunta
What is the Instruction Level Parallelism?
Respuesta
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Pregunta 125
Pregunta
What is the RLP?
Respuesta
-
Random Level Parallelism
-
Request Level Parallelism
-
Research Level Parallelism
Pregunta 126
Pregunta
In multilevel caches “Global miss rate” equals:
Respuesta
-
misses in cache / CPU memory accesses
-
misses in cache / accesses to cache
-
misses in cache / number of instructions
Pregunta 127
Pregunta
What does mean MSHR?
Respuesta
-
Miss Status Handling Register
-
Memory status handling register
-
mips status hardware prefetching
-
map status handling reload
Pregunta 128
Pregunta
What is the spatial locality?
Respuesta
-
Exploit by remembering the contents of recently accessed locations
-
Exploit by fetching blocks of data around recently accessed locations
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