O GoConqr está de visual novo! Conte para nós o que você achou.

Mapa mental

Design Verification

ALEJANDRA HEREDIA MENDEZ Espanhol

Design Verification

Conteúdo do mapa

Design Verification

  1. How to verify the correctness of your programs?

  2. As a program's logic becomes more complex, it is increasingly important to verify its correctness

  3. SELECTING VERIFICATION METHODS

    • DEFECT PROFILE
      • Defect experience
      • Focus on those areas that cause you the most trouble.
    • VERIFICATION EFFECTIVENESS
      • You should identify a family of effective verification techniques
        • Make a practice of using them
    • VERIFICATION ECONOMICS
      • You must learn which verification method work best for you and the conditions under which they work.
  4. DESIGN STANDARDS

    • PRODUCT CONVENTIONS
      • Essential if multiple developers are to produce a system that has any external coherence
        • User Interfaces
        • External naming
        • System error handling
        • Installation procedures
        • Help facilities
    • PRODUCT DESIGN STANDARDS
      • Calling and naming conventions
      • Header standards
      • Test standards
      • Documentation formats
    • REUSE STANDARDS
      • They must be properly managed
        • Think about reuse during design / design reviews
      • They can substantially improve your productivity
  5. VERIFICATION METHODS

    • SYMBOLIC EXECUTION
      • It covers all symbolic values rather than merely a few tested cases
      • Provides a structured and theoretically sound way to logically verify programs
    • PROOF BY INDUCTION
      • Applies to logical expressions with integer parameters.
      • You start by showing that the logic of a program is true for a base case
  6. VERIFYING THE OBJECT STATE MACHINE

    • Check for hidden traps or loops
    • Check for all possible states
    • Check for state orthogonality
    • Check for complete transitions
  7. PROGRAM TRACING

    • EXECUTION TABLES
      • Provides an orderly way to check the logic flow in a Logic Specification Template
        • You list the logic steps in order together with the variable and parameters values for each case to be examined.
          • When loops are encountered, their instructions are repeated until the cycle is completed.
      • Time consuming
        • Reliable
          • Simple
    • TRACE TABLES
      • More efficient for verifying logic correctness
        • Involves three complementary techniques:
          • Symbolic Execution
          • Trace table examination of all possible cases
          • Proof by induction
  8. VERIFYING PROGRAM CORRECTNESS

    • TESTING LOOPS
      • For-loop Verification
      • While-loop Verification
      • Repeat-until Verification
  9. COMMENTS ON VERIFICATION METHODS

    • DESIGN VERIFICATION STRATEGY
      • You should design down and verify up.
    • SPECIFICATION CONFORMANCE
      • Consider all possible logic cases and verify that they're correctly handled.
    • VERIFICATION COMPLEXITY
      • Track the time verification takes and the degree to which it helps you to find design defects
    • FORMAL VERIFICATION METHODS
      • Best used during program design.
      • Human-intensive, subject to error.
      • You must practice each method until you're reasonably proficient.

Imagens e arquivos do mapa

  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification
  • Design Verification

Informações

Descrição
Mapa Mental sobre Design Verification, criado por ALEJANDRA HEREDIA MENDEZ em 19-10-2020.
Visualizações
13
Avaliação

Fale Conosco

Sobre o que é sua mensagem?

O que você acha do novo visual?

Você gostou?