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PCA_Final [arc2-1, Part-2]

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Arxitektura - gavno
Good Guy Beket
Quiz por Good Guy Beket, atualizado more than 1 year ago
Good Guy Beket
Criado por Good Guy Beket quase 6 anos atrás
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Resumo de Recurso

Questão 1

Questão
What is a Latency:
Responda
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is amount of data that can be in flight at the same time (Little’s Law)

Questão 2

Questão
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • n loop iterations
  • subroutine call
  • vector access

Questão 3

Questão
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • subroutine call
  • n loop iterations
  • vector access

Questão 4

Questão
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • subroutine call
  • n loop iterations
  • vector access

Questão 5

Questão
Cache HIT:
Responda
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Questão 6

Questão
Cache MISS:
Responda
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Questão 7

Questão
Average Memory Access Time is equal:
Responda
  • Hit Time * ( Miss Rate + Miss Penalty )
  • Hit Time - ( Miss Rate + Miss Penalty )
  • Hit Time / ( Miss Rate - Miss Penalty )
  • Hit Time + ( Miss Rate * Miss Penalty )

Questão 8

Questão
The formula of “Iron Law” of Processor Performance:
Responda
  • time/program = instruction/program * cycles/instruction * time/cycle
  • time/program = instruction/program * cycles/instruction + time/cycle
  • time/program = instruction/program + cycles/instruction * time/cycle

Questão 9

Questão
Structural Hazard:
Responda
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • An instruction depends on a data value produced by an earlier instruction
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Questão 10

Questão
Data Hazard:
Responda
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Questão 11

Questão
Control Hazard:
Responda
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline

Questão 12

Questão
What is a Bandwidth:
Responda
  • a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is amount of data that can be in flight at the same time (Little’s Law)

Questão 13

Questão
What is a Bandwidth-Delay Product:
Responda
  • is amount of data that can be in flight at the same time (Little’s Law)
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle

Questão 14

Questão
What is Computer Architecture?
Responda
  • is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
  • is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
  • the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them

Questão 15

Questão
Least Recently Used (LRU):
Responda
  • cache state must be updated on every access
  • Used in highly associative caches
  • FIFO with exception for most recently used block(s)

Questão 16

Questão
Cache Hit -
Responda
  • Write Through – write both cache and memory, generally higher traffic but simpler to design
  • Write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
  • No Write Allocate – only write to main memory

Questão 17

Questão
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Responda
  • If cache size is doubled, miss rate usually drops by about √2
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
  • None of them

Questão 18

Questão
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Responda
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
  • If cache size is doubled, miss rate usually drops by about √2
  • None of them

Questão 19

Questão
What is the access time?
Responda
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • None of them

Questão 20

Questão
What is the cycle time?
Responda
  • The minimum time between requests to memory.
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of them

Questão 21

Questão
What does SRAM stands for?
Responda
  • Static Random Access memory
  • System Random Access memory
  • Short Random Access memory
  • None of them

Questão 22

Questão
What does DRAM stands for?
Responda
  • Dynamic Random Access memory
  • Dual Random Access memory
  • Dataram Random Access memory

Questão 23

Questão
Which one is concerning to fallacy?
Responda
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Questão 24

Questão
Which one is NOT concerning to pitfall?
Responda
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Questão 25

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
Responda
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command
  • The time from the reception of the response until the user begins to enter the next command

Questão 26

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
Responda
  • The time from the reception of the response until the user begins to enter the next command
  • The time for the user to enter the command
  • The time between when the user enters the command and the complete response is displayed

Questão 27

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Responda
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Questão 28

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Responda
  • Average time per task in the queue
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Questão 29

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time system” -
Responda
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue

Questão 30

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length server” -
Responda
  • Average number of tasks in service
  • Average length of queue

Questão 31

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
Responda
  • Average length of queue
  • Average number of tasks in service

Questão 32

Questão
Select two-dimensional interconnection network
Responda
  • Mesh
  • Linear Array
  • Cross Bar

Questão 33

Questão
Select multi-dimensional interconnection network
Responda
  • Linear Array
  • Cross Bar
  • Cube

Questão 34

Questão
Select multi-dimensional interconnection network
Responda
  • Linear Array
  • Cross Bar
  • Hyper Cube

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