CSA IITU Part 1 (235)

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Quiz on CSA IITU Part 1 (235), created by Hello World on 12/20/2017.
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Quiz by Hello World, updated more than 1 year ago
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Resource summary

Question 1

Question
130. How many bytes equals Petabyte (PB)?
Answer
  • · Quadrillion
  • · Million
  • · Trillion
  • · Billion
  • · 1000

Question 2

Question
129. Which one of the following is a memory whose duty is to store most frequently used data?
Answer
  • · Main memory
  • · Cache
  • · ROM
  • · Auxiliary memory
  • · PROM

Question 3

Question
128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
Answer
  • · Binary Adder
  • · Full Adder
  • · Half Adder
  • · Adder
  • · OR gate

Question 4

Question
127. The key technology used in IV generation computers is ___.
Answer
  • · MSI
  • · SSI
  • · LSI & VLSI
  • · Transistors
  • · Vacuum Tubes

Question 5

Question
126. The computer architecture having stored program is ___.
Answer
  • · Harvard
  • · Von Neumann
  • · Pascal
  • · Ada
  • · Cobol

Question 6

Question
125. Stack is a ___list.
Answer
  • · FIFO
  • · LIFO
  • · FILO
  • · OFLI

Question 7

Question
124. CACHE memory is implemented using ___.
Answer
  • · Dynamic RAM
  • · Static RAM
  • · EA RAM
  • · ED RAM
  • · EP RAM

Question 8

Question
123. What does D stand for in a D flip-flop?
Answer
  • · Direct
  • · Don’t care
  • · Data
  • · Device
  • · Disk

Question 9

Question
104. What is a Capacity?
Answer
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · first-reference to a block, occur even with infinite cache
  • · misses that occur because of collisions due to less than full associativity

Question 10

Question
103. What is a Compulsory?
Answer
  • · first-reference to a block, occur even with infinite cache
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · misses that occur because of collisions due to less than full associativity

Question 11

Question
39. 74. How many elements of the Instruction Set Architecture (ISA)
Answer
  • 8
  • 7
  • 6

Question 12

Question
38. 73. What is the MISD one of the categories of computers?
Answer
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Set Data Stream

Question 13

Question
36. 72. What is the Instruction Level Parallelism
Answer
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Question 14

Question
35. 71. What is the Request Level Parallelism
Answer
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Question 15

Question
34. 70. What is the Thread Level Parallelism
Answer
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Question 16

Question
33. 69. What is the Vector Architectures and Graphic Processor Units (GPUs)
Answer
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Question 17

Question
32. 68. The Application of Brokerage operations how many cost of downtime per hour?
Answer
  • 8.870.000$
  • 7.550.000$
  • 6.450.000$

Question 18

Question
31. 67. What is the PMD in computer classes?
Answer
  • Percentage map device
  • Personal mobile device
  • Peak maze development
  • Powerful markup distance

Question 19

Question
30. 66. Which distance of price has Clusters/warehouse-scale computers?
Answer
  • 100 – 100.000$
  • 100.000 – 200.000.000$
  • 5.000 – 10.000.000$

Question 20

Question
29. 65. How many classes of computers classified?
Answer
  • 7
  • 3
  • 5

Question 21

Question
28. 64. What is the RLP?
Answer
  • Request Level Parallelism
  • Research Level Parallelism
  • Random Level Parallelism

Question 22

Question
27. 63. How much in percentage single-processor performance improvement has dropped to less than?
Answer
  • 22%
  • 33%
  • 11%

Question 23

Question
26. 62. When single-processor performance improvement has dropped?
Answer
  • 2003
  • 2002
  • 2004

Question 24

Question
25. 61. What is a RISC computers?
Answer
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer
  • Reduced Instruction Set Computer

Question 25

Question
24. 56. Choose the right formula of AMAT(в базе был неверный ответ можете попробовать подать апелляцию)
Answer
  • Average Memory Access time = Hit Time + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Time + Miss time * Miss penalty
  • Average Memory Access time = Hit Rate + Miss time * Miss penalty

Question 26

Question
23. What is the total number of writes that hit in the cache?
Answer
  • 588
  • 784
  • 12.5%
  • 0.25%

Question 27

Question
22. 30. Definition of Block address:
Answer
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • time to access upper level
  • memory closer to processor

Question 28

Question
20. 28. Definition of Block:
Answer
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • memory closer to processor
  • time to access upper level

Question 29

Question
19. 27. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
Answer
  • SRAM
  • DRAM
  • RAM

Question 30

Question
18. 26. Performance of a machine is determined by:
Answer
  • Instruction count, Clock cycle time, Correlating predictors
  • Instruction count, Clock cycle time, Clock cycle per instruction
  • Clock cycle time, Correlating predictors, Aggressive instruction
  • Clock cycle time, Clock cycles per instruction, Correlating Predictors

Question 31

Question
17. 25. Pipe-lining is a unique feature of ___.
Answer
  • CISC
  • IANA
  • ISA
  • RISC

Question 32

Question
16. 24. The iconic feature of the RISC machine among the following are
Answer
  • Increased memory size
  • Reduced number of addressing modes
  • Having a branch delay slot
  • All of the above

Question 33

Question
15. 23. The Sun micro systems processors usually follow ___ architecture.
Answer
  • CISC
  • ISA
  • ULTRA SPARC
  • RISC

Question 34

Question
14. 22. Of the following, identify the memory usually written by the manufacturer.
Answer
  • RAM
  • DRAM
  • SRAM
  • ROM
  • Cache Memory

Question 35

Question
13. 21. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
Answer
  • Hit rate
  • Miss rate
  • Access rate
  • Success rate

Question 36

Question
12. 20. How many instructions can be implemented in MIPS?
Answer
  • 2 clock cycles
  • 3 clock cycles
  • 4 clock cycles
  • 5 clock cycles

Question 37

Question
19. The secondary effect that results from instruction scheduling in large code segments is called ___?
Answer
  • Aggressive instruction
  • Correlating predictors
  • Register predictors
  • Register pressure

Question 38

Question
10. 18. The CISC stands for?
Answer
  • Computer Instruction Set Compliment
  • Complete Instruction Set Compliment
  • Computer Indexed Set Components
  • Complex Instruction Set Computer

Question 39

Question
9. Assembly line operation is also called as?
Answer
  • Pipelining process
  • Superscalar operation
  • None of the mentioned
  • Von Neumann cycle

Question 40

Question
8. 16. Can you solve the Dining Philosophers’ Problem using monitors?
Answer
  • Yes
  • No
  • Yes, but only if there are less than five philosophers
  • No, unless there are more than five philosophers

Question 41

Question
7. 15. The central themes of operating system design are all concerned with the management of processes and threads?
Answer
  • Multiprogramming, multiprocessing, distributed processing
  • Multitasking, multiprogramming, multithreading
  • Multiprocessing, uniprocessing, multitasking
  • Multithreading, distributed processing, uniprocessing

Question 42

Question
6. 14. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Answer
  • Availability, confidentiality, data integrity, authenticity
  • Safety, accountability, reliability, density
  • Usability, integrity, confidentiality, reliability
  • Flexibility, availability, accountability, authenticity

Question 43

Question
5. 13. Which of the following principles has Deadlock?
Answer
  • Execution, Association, Starvation
  • Prevention, Avoidance, Detection
  • Starvation, Detection, Exclusion
  • Exclusion, Avoidance, Starvation

Question 44

Question
4. 12. How many principles has Deadlock?
Answer
  • 3
  • 5
  • 2
  • 6

Question 45

Question
3. 11. Three techniques are possible for I/O operations:
Answer
  • Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
  • Machine I/O, Architecture I/O, Hardware I/O
  • Object-oriented I/O, Design I/O, Usable I/O
  • Control I/O, Status I/O, Transfer I/O

Question 46

Question
2. 10. Cache Design has these properties?
Answer
  • Size, search function, write function, read policy, vector algorithm
  • Size, mapping algorithm, vector function, write policy, replacement function
  • Size, blocking algorithm, search function, replacement vector, read policy
  • Size, block size, mapping function, replacement algorithm, write policy

Question 47

Question
1. In Memory Hierarchy, at the Inboard storage which of the following are included:
Answer
  • Magnetic disk
  • Magnetic tape
  • Optical disk
  • Main memory

Question 48

Question
180. In Memory Hierarchy, at the Off-line storage which of the following are included:
Answer
  • • Cache
  • • Magnetic disk
  • • Magnetic tape
  • • Main memory

Question 49

Question
179. In Memory Hierarchy, at the Outboard storage which of the following are included:
Answer
  • • Cache
  • • Main memory
  • • Magnetic tape
  • • Magnetic disk

Question 50

Question
178. How many parts of Memory Hierarchy?
Answer
  • • 5
  • • 4
  • • 2
  • • 3

Question 51

Question
177. Which one is concerning to fallacy?
Answer
  • o Predicting cache performance of one program from another
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs

Question 52

Question
176. Which one is NOT concerning to pitfall?
Answer
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs
  • o Predicting cache performance of one program from another

Question 53

Question
175. ChoosetheEleventhOptimization
Answer
  • o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • o None of them

Question 54

Question
174. ChoosetheEightOptimization
Answer
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Critical word first
  • o Nonblocking Caches to Increase Cache Bandwidth
  • o Trace Caches to Reduce Hit Time

Question 55

Question
173. Choose the strategy of Seventh Optimization.
Answer
  • o Critical restart
  • o Critical word first
  • o Sequential inter leaving
  • o Merging Write Buffer to Reduce Miss Penalty

Question 56

Question
172. Choose the benefit of Cache Optimization.
Answer
  • o Larger block size to reduce miss rate
  • o Bigger caches to increase miss rat
  • o Single level caches to reduce miss penalty
  • o None of them

Question 57

Question
171. What is conflict in Cs model?
Answer
  • o If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o None of them

Question 58

Question
170. What is capacityin Cs model?
Answer
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them

Question 59

Question
169. What is the compulsory in Cs model?
Answer
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Question 60

Question
168. How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Answer
  • o the number of prediction entries selected by the branch = 1K.
  • o the number of prediction entries selected by the branch = 2K.
  • o the number of prediction entries selected by the branch = 8K.
  • o the number of prediction entries selected by the branch = 4K.

Question 61

Question
167. Branch predictors that use the behavior of other branches to make a prediction are called
Answer
  • o correlating predictors or two-level predictors
  • o branch-prediction buffer
  • o branch table
  • o three level loop

Question 62

Question
166. The simplest dynamic branch-prediction scheme is a
Answer
  • o branch-prediction buffer
  • o branch buffer
  • o All answers correct
  • o registrationo registration

Question 63

Question
165. Effect that results from instruction scheduling in large code segments is called…?
Answer
  • o register pressure
  • o loop unrolling
  • o loop-level
  • o registration

Question 64

Question
164. A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Answer
  • o loop unrolling
  • o RAR
  • o loop-level
  • o loop rolling

Question 65

Question
163. What is given is not a hazard?
Answer
  • o RAR
  • o WAR
  • o WAW
  • o LOL

Question 66

Question
162. What is RAW (read after write)?
Answer
  • o when j tries to read a source before i writes it, so j incorrectly gets the old value
  • o when j tries to write a source before i writes it
  • o when i tries to read a source before j writes it, so j correctly gets the old value
  • o when a tries to write a source before b read it, so a incorrectly gets the old value

Question 67

Question
161. When occurs an output dependence?
Answer
  • o When i and instruction j write the same register or memory location
  • o when i and instruction j write the same adress or memory location
  • o when i and instruction j write the same name
  • o All answers is correct

Question 68

Question
160. What is Name dependence?
Answer
  • o name dependence occurs when two instructions use the same register or memory location
  • o name dependence occurs when five or more instructions use the same register or memory location
  • o name dependence occurs when instructions use the same name
  • o All answers is correct

Question 69

Question
159. In parallelism have three different types of dependences, tagging him:
Answer
  • o data dependences , name dependences , and surname dependences
  • o datagram dependences , name dependences , and animal dependences
  • o no correct answers
  • o data dependences , name dependences , and control dependences

Question 70

Question
158. The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Answer
  • o loop-level parallelism
  • o exploit-level parallelism
  • o high-level minimalism
  • o low-level minimalism

Question 71

Question
157. The simplest and most common way to increase the ILP is …?
Answer
  • o to exploit parallelism among iterations of a loop
  • o to exploit minimalism among iterations of a loop
  • o to destroy iterations of a loop
  • o to decrease the minimalism of risk

Question 72

Question
156. What is the Pipeline CP = ?
Answer
  • o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • o deal pipeline CPU + Data hazard stalls + Control stalls
  • o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
  • o Structural stalls + Data hazard stalls + Control stalls

Question 73

Question
155. The ideal pipeline CPI is a measure of …
Answer
  • o the maximum performance attainable by the implementation
  • o the maximum performance attainable by the instruction
  • o the minimum performance attainable by the implementation
  • o the minimum performance attainable by the instruction

Question 74

Question
154. How to decrypt RISC?
Answer
  • o Reduced Instruction Set Computer
  • o Recall Instruction Sell Communication
  • o Rename Instruction Sequence Corporation
  • o Red Instruction Small Computer

Question 75

Question
153. What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Answer
  • o Address aliasing prediction
  • o Branch prediction
  • o Integrated branch prediction
  • o Dynamic branch prediction

Question 76

Question
152. Which is not the function of integrated instruction fetch unit:
Answer
  • o Instruction memory commit
  • o Integrated branch prediction
  • o Instruction memory access and buffering
  • o Instruction prefetch

Question 77

Question
151. Buffering the actual target instructions allows us to perform an optimization which called:
Answer
  • o branch folding
  • o Branch prediction
  • o Target instructions
  • o Target address

Question 78

Question
150. A branch-prediction cache that stores the predicted address for the next instruction after a branch
Answer
  • o branch-target buffer
  • o data buffer
  • o frame buffer
  • o optical buffer

Question 79

Question
149. Examples of VLIW/LIW:
Answer
  • o TI C6x
  • o MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5

Question 80

Question
148. Examples of superscalar(dynamic) :
Answer
  • o None at the present
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o MIPS and ARM
  • o TI C6x

Question 81

Question
147. Examples of superscalar(static):
Answer
  • • MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Question 82

Question
146. Examples of EPIC:
Answer
  • o Itanium
  • o MIPS and ARM
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Question 83

Question
145. Which Multiple-issue processors has not the hardware hazard detection:
Answer
  • o EPIC
  • o Superscalar(dynamic)
  • o Superscalar(static)
  • o Superscalar(speculative)

Question 84

Question
144. Which one is not the major flavor of Multiple-issue processors:
Answer
  • o statistically superscalar processors
  • o dynamically scheduled superscalar processors
  • o statically scheduled superscalar processors
  • o VLIW (very long instruction word) processors

Question 85

Question
143. Choose the steps of instruction execution:
Answer
  • o issue, execute, write result, commit
  • o execution, commit, rollback
  • o issue, execute, override, exit
  • o begin, write, interrupt, commit

Question 86

Question
142. Choose correct fields of entry in the ROB:
Answer
  • o the instruction type, the destination field, the value field, and the ready field
  • o the source type, the destination field, the value field, and the ready field
  • o the program type, the ready field, the parameter field, the destination field
  • o the instruction type, the destination field, and the ready field

Question 87

Question
141. How many fields contains the entry in the ROB:
Answer
  • 4
  • 6
  • 5
  • 3

Question 88

Question
140. For what the reorder buffer is used :
Answer
  • o To pass parameters through instructions that may be speculated
  • o To pass results among instructions that may be speculated.
  • o To get additional registers in the same way as the reservation stations
  • o To control registers

Question 89

Question
139. How this process called: “Operations execute as soon as their operands are available”
Answer
  • o data flow execution
  • o data control execution
  • o instruction execution
  • o instruction field execution

Question 90

Question
138. Which of these is NOT characteristics of recent highperformance microprocessors?
Answer
  • o Color
  • o Functional unit capability
  • o Clock rate
  • o Power

Question 91

Question
• Popular data structure for organizing a large collection of data items so that one can quickly
Answer
  • o Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • o Popular tables for organizing a large collection of data structure
  • o Popular data structure for updating large collections, so that one can hardly answer questions
  • o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Question 92

Question
136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Answer
  • o Achievable ILP with software resource constraints
  • o Limited ILP due to software dependences
  • o Achievable ILP with hardware resource constraints
  • o Variability of ILP due to software and hardware interaction

Question 93

Question
135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Answer
  • o Dynamic power
  • o Processing rate
  • o Static power
  • o Processor state

Question 94

Question
134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Answer
  • o Static power
  • o Dynamic power
  • o Processing rate
  • o Processor state

Question 95

Question
133. If we want to sustain four instructions per clock
Answer
  • o We must fetch more, issue more, and initiate execution on more than four instructions
  • o We must fetch less, issue more, and initiate execution on more than two instructions
  • o We must fetch more, issue more, and initiate execution on less than five instructions
  • o We must fetch more, issue less, and initiate execution on more than three instructions

Question 96

Question
132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
Answer
  • o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
  • o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
  • o The number of transistors switching will be proportional to the sustained rate
  • o The performance is proportional to the peak issue rate

Question 97

Question
131. Which of the written below is NOT increase power consumption?
Answer
  • o Increasing multithreading
  • o Increasing performance
  • o Increasing multiple cores
  • o Increasing multithreading(повторяется хз что тут )

Question 98

Question
130. Which of the following descriptions corresponds to dynamic power?
Answer
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Certainly a design concern
  • o None of the above

Question 99

Question
129. Which of the following descriptions corresponds to static power?
Answer
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Proportional to the product of the number of switching transistors and the switching rate Probability
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o All of the above

Question 100

Question
128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Answer
  • o Speedup
  • o Efficiency
  • o Probability
  • o Ration

Question 101

Question
127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Answer
  • • 90% 10%
  • o 70% 30%
  • o 50% 50%
  • o 89% 11%

Question 102

Question
126. What MTTF means:
Answer
  • o mean time to failure
  • o mean time to feauture
  • o mean this to failure
  • o my transfers to failure

Question 103

Question
125. Desktop benchmarks divide into __ broad classes:
Answer
  • o two
  • o three
  • o four
  • o five

Question 104

Question
124. Systems alternate between two states of service with respect to an SLA:
Answer
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Question 105

Question
123. The most companies spend only ____________ of their income on R&D, which includes all engineering.
Answer
  • o 30% to 48%
  • o 4% to 12%
  • o 15% to 30%
  • o 1% to 17%

Question 106

Question
122. Volume is a ________ key factor in determining cost.
Answer
  • o second
  • o first
  • o fifth
  • o third

Question 107

Question
121. Manufacturing costs that decrease over time are ____
Answer
  • o the learning curve
  • o the cycled line
  • o the regular option
  • o the final loop

Question 108

Question
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
Answer
  • o dynamic power
  • o physical energy
  • o constant supply
  • o simple battery

Question 109

Question
119. Integrated circuit processes are charecterized by the
Answer
  • o feature size
  • o permanent size n
  • o compex size
  • o fixed size

Question 110

Question
118. Products that are sold by multiple vendors in large volumes and are essentialy identical
Answer
  • o boxes
  • o files
  • o folders
  • o commodities

Question 111

Question
117. Learning curve itself is best measured by change in...
Answer
  • o bytes
  • o bits
  • o seconds
  • o yeld

Question 112

Question
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Answer
  • o bandwidth
  • o throughput
  • o latency
  • o performance

Question 113

Question
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Answer
  • o bandwidth
  • o latency
  • o throughput
  • o performance

Question 114

Question
1. Network performance depends of what?
Answer
  • o performance of swithes and transmission system
  • o performance of switches
  • o has no dependensies
  • o performance of transmission system

Question 115

Question
113. What is a “Kernel” in Cache Memory?
Answer
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables
  • o Execution in user code

Question 116

Question
112. What is a “Synchronization” in Cache Memory?
Answer
  • o Execution in user code
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables

Question 117

Question
111. What is a “Kernel” in Cache Memory?
Answer
  • o Execution or waiting for synchronization variables
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code

Question 118

Question
110. What is a “Synchronization” in Cache Memory?
Answer
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code
  • o Execution or waiting for synchronization variables
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