PCA_Final [arc2-1, Part-1]

Good Guy Beket
Quiz by Good Guy Beket, updated more than 1 year ago
Good Guy Beket
Created by Good Guy Beket over 1 year ago
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Arc2-1 file's quiz
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Resource summary

Question 1

Question
Storage Systems, “Higher associativity to reduce miss rate”
Answer
  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses

Question 2

Question
How many Optimizations’ in Cache memory Performance?
Answer
  • 6
  • 8
  • 10

Question 3

Question
Storage Systems, “Larger block size to reduce miss rate”
Answer
  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses

Question 4

Question
What is the “Read Operands” in simple five-stage pipeline?
Answer
  • Wait until no data hazards, then reads the operand
  • Decode instructions, check for structural hazards

Question 5

Question
Storage Systems, “Bigger caches to reduce miss rate”
Answer
  • The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses

Question 6

Question
Tenth optimization of Cache Memory “Register prefetch”?
Answer
  • Loads data only into the cache and not the register
  • Will load the value into register

Question 7

Question
At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”?
Answer
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Faults in software (usually) and hardware design (occasionally)
  • Mistakes by operations and maintenance personnel

Question 8

Question
What is a “Kernel” in Cache Memory?
Answer
  • Execution or waiting for synchronization variables
  • Execution in user code
  • Execution in the OS that is neither idle nor in synchronization access

Question 9

Question
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Answer
  • Average time per task in the queue
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Question 10

Question
How many steps took Virtual Machine Monitor to improve performance of virtual machines?
Answer
  • 5
  • 3
  • 4

Question 11

Question
How many issue queue used in Centralized Superscalar 2 and Exceptions
Answer
  • 4
  • 3
  • 2
  • 1

Question 12

Question
Which of the following formula is true about Issue Queue for “Instruction Ready”
Answer
  • Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
  • Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards

Question 13

Question
What is the “Read Operands” in Pipelining Basics?
Answer
  • Wait until no control hazards, then reads the operand
  • Wait until no structural hazards, then reads the operand
  • Wait until no data hazards, then reads the operand

Question 14

Question
Perfect caches at The Hardware Model?
Answer
  • All memory accesses take one clock cycle
  • All conditional branches are predicted exactly
  • All memory addresses are known exactly

Question 15

Question
How many stages used in Superscalar (Pipeline)?
Answer
  • 4
  • 5
  • 6
  • 7

Question 16

Question
How much in percentage single-processor performance improvement has dropped to less than?
Answer
  • 22%
  • 33%
  • 11%

Question 17

Question
What is “VLIW”?
Answer
  • Very Long Instruction Word
  • Very Less Interpreter Word
  • Very Light Internal Word
  • Very Low Invalid Word

Question 18

Question
At VLIW by “performance and loop iteration” which time is shorter?
Answer
  • Software Pipelined
  • Loop Unrolled

Question 19

Question
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Answer
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Question 20

Question
What single-processor performance improvement has dropped?
Answer
  • 2004
  • 2002
  • 2003

Question 21

Question
What does MAF?
Answer
  • Miss Address File
  • Map Address File
  • Memory Address File

Question 22

Question
How many classes of computers classified?
Answer
  • 3
  • 5
  • 7

Question 23

Question
Sixth Optimization of Cache Memory “Critical word first”?
Answer
  • Fetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Question 24

Question
In an important early study of intrusion, Anderson[ANDE80] identified three classes of intruders:
Answer
  • Control, exploit, system
  • Masquerader, misfeasor, clandestine user
  • Individual, legitimate, authorized
  • Outside, inside, offside

Question 25

Question
How many elements of the Instruction Set Architecture (ISA):
Answer
  • 7
  • 8

Question 26

Question
What is the “Bigger caches to reduce miss rate” at Basics of Memory Hierarchies
Answer
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses

Question 27

Question
At storage systems Gray and Siewiorek classify faults what does mean “Design faults”?
Answer
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Faults in software (usually) and hardware design (occasionally)
  • Mistakes by operations and maintenance personnel

Question 28

Question
What is the ARF?
Answer
  • Architectural Register File
  • Architecture Relocation File
  • Architecture Reload File
  • Architectural Read File

Question 29

Question
What is the Conflict in main categories in Cache Memory?
Answer
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Question 30

Question
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is?
Answer
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Question 31

Question
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Answer
  • Width and Lifetime
  • Width and Height
  • Time and Cycle
  • Length and Addition

Question 32

Question
What is a “Synchronization” in Cache Memory?
Answer
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code
  • Execution or waiting for synchronization variables

Question 33

Question
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is?
Answer
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Question 34

Question
Flash memory is a type of?
Answer
  • Electronically Erasable Programmable Read-Only Memory
  • Electronically Extensible Programmable Re-Order Memory
  • Electronically Executable Programmable Reduce Memory

Question 35

Question
Access time at memory latency is -
Answer
  • The time between when a read is requested and when the desired word arrives
  • The minimum time between unrelated requests to memory

Question 36

Question
In Multilevel Caches “Local miss rate” equals =
Answer
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses
  • misses in cache / number of instructions

Question 37

Question
What is a RAID 1?
Answer
  • Also called mirroring or shadowing, there are two copies of every piece of data
  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
  • This organization was inspired by applying memory-style error correcting codes to disks

Question 38

Question
RAW (read after write)?
Answer
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard arises n antidependence (or name dependence)

Question 39

Question
How many size of Cache L3 is true approximately?
Answer
  • 3 MB
  • 256 MB
  • 256 KB

Question 40

Question
What is a RAID 3?
Answer
  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
  • Many applications are dominated by small accesses
  • Also called mirroring or shadowing, there are two copies of every piece of data

Question 41

Question
What is the increasing cache bandwidth?
Answer
  • Critical word first and merging write buffer
  • Pipelined caches, multibanked caches and non-blocking caches
  • Small and simple first-level caches and way-prediction

Question 42

Question
What is RAID 2?
Answer
  • This organization was inspired by applying memory-style error correcting codes to disks
  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
  • Also called mirroring or shadowing, there are two copies of every piece of data

Question 43

Question
In Non-Blocking Caches what does mean “Critical word first”?
Answer
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

Question 44

Question
Sixth optimization of cache memory “Early restart”?
Answer
  • Fetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Question 45

Question
How many size of Cache L2 is true approximately?
Answer
  • 256 KB
  • 4 KB
  • 32 MB

Question 46

Question
Reducing the miss penalty or miss rate via parallelism?
Answer
  • Hardware prefetching and compiler prefetching
  • Compiler optimization
  • Pipelined caches, multibanked caches and non-blocking caches

Question 47

Question
What is a RT?
Answer
  • Rename Table
  • Recall Table
  • Relocate Table
  • Remove Table

Question 48

Question
How many functions at integrated instruction fetch units?
Answer
  • 3
  • 4
  • 5

Question 49

Question
What is the PMD in computer classes?
Answer
  • Percentage map device
  • Personal mobile device
  • Powerful markup distance
  • Peak maze development

Question 50

Question
The second type of dependence is?
Answer
  • Data dependence
  • Name dependence
  • Control dependence

Question 51

Question
How many elements presented at performance trends: bandwidth over latency?
Answer
  • 4
  • 5
  • 3

Question 52

Question
What is the compulsory in main categories in cache memory?
Answer
  • Cache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)
  • Misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • First-reference to a block, occurs even with infinite cache

Question 53

Question
How many elements in trends of technology?
Answer
  • 5
  • 4
  • 6

Question 54

Question
Perfect memory address alias analysis at the Hardware model?
Answer
  • All conditional branches are predicted exactly
  • All memory accesses take one clock cycle
  • All memory addresses are known exactly

Question 55

Question
Speculating on exceptions “Recovery mechanism” is –
Answer
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • Only write architectural state at commit point, so can throw away partially executed instructions after exception
  • None of them
  • An entity capable of accessing objects

Question 56

Question
What is the reducing the miss rate?
Answer
  • What is the reducing the miss rate?
  • Performance optimization
  • Compiler optimization
  • Time optimization

Question 57

Question
DDR is –
Answer
  • Double data rate
  • Density data rate
  • Dynamic data rate

Question 58

Question
In Non-blocking caches what does mean “Early restart”?
Answer
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Question 59

Question
Which distance of price has clusters/warehouse-scale computers?
Answer
  • 100-100 000$
  • 100 000-200 000 000$
  • 5 000 -10 000 000$

Question 60

Question
Little’s Law and a series of definitions lead to several useful equations for “Time System”-
Answer
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
  • Average time per task in the queue

Question 61

Question
What is the MISD one of the categories of computers?
Answer
  • Multiple instructions streams, set data stream
  • Multiple instructions streams, single data stream
  • Multiple instruction stream, multiple data streams

Question 62

Question
What is a RAID 4?
Answer
  • Many applications are dominated by small accesses
  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
  • Also called mirroring or shadowing, there are two copies of every piece of data

Question 63

Question
Tenth Optimization of cache memory “Cache prefetch”?
Answer
  • Will load the value into a register
  • Loads data only into the cache and not the register

Question 64

Question
What is the Request level parallelism?
Answer
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or the operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Question 65

Question
Non-blocking cache timeline for “Hit under miss” the sequence is -?
Answer
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Question 66

Question
At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”?
Answer
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Faults in software (usually) and hardware design (occasionally)
  • Mistakes by operations and maintenance personnel

Question 67

Question
WAR(write after read)?
Answer
  • This hazard correspond to an output dependence
  • This hazard arises from an antidependence (or name dependence)

Question 68

Question
Main term of dependability is SLAs?
Answer
  • Scale level approach
  • Service level agreements
  • Standard level achievement

Question 69

Question
At VLIW by “performance and loop iteration” which time is longer?
Answer
  • Loop unrolled
  • Software Pipelined

Question 70

Question
What is the temporal locality?
Answer
  • Exploit by remembering the contents of recently accessed locations
  • Exploit by fetching blocks of data around recently accessed locations

Question 71

Question
What is an IQ?
Answer
  • Issue Queue
  • Internal Queue
  • Interrupt Queue
  • Instruction Queue

Question 72

Question
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time”-?
Answer
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command
  • The time from the reception of the response until the user begins to enter the next command

Question 73

Question
How many size of Cache L1 is true approximately?
Answer
  • 8 KB
  • 256 KB
  • 2 MB

Question 74

Question
What is a RISC computers?
Answer
  • Reduced instruction set computer
  • Research interconnect several computer
  • Rational interruptible security computer

Question 75

Question
The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
Answer
  • 4
  • 6
  • 5

Question 76

Question
What is the “opcode”?
Answer
  • Operand code
  • Optional code
  • Operation code

Question 77

Question
WAW(write after write)?
Answer
  • This hazard arises from an antidependence (or name dependence)
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence

Question 78

Question
What is the Vector Architectures and graphic processor units(GPUs)?
Answer
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution

Question 79

Question
Speculating on exceptions “Check prediction mechanism” is –
Answer
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • The way in which an object is accessed by a subject
  • None of them

Question 80

Question
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Answer
  • Speculative operations that don’t cause exceptions
  • Hardware to check pointer hazards

Question 81

Question
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:
Answer
  • Speculative operations that don’t cause exceptions
  • Hardware to check pointer hazards

Question 82

Question
What is PRF?
Answer
  • Pipeline Register File
  • Physical Register File
  • Pure Register File
  • Pending Register File

Question 83

Question
Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?
Answer
  • 3
  • 4
  • 2

Question 84

Question
How many instructions used in Distributed Superscalar 2 and Exceptions?
Answer
  • 1
  • 2
  • 3
  • 4

Question 85

Question
What is about Superscalar means “F-D-X-M-W”?
Answer
  • Fetch, Decode, Instruct, Map, Write
  • Fetch, Decode, Excite, Memory, Write
  • Fetch, Decode, Except, Map, Writeback
  • Fetch, Decode, Execute, Memory, Writeback

Question 86

Question
SDRAM is -
Answer
  • Synchronous dynamic random access memory
  • Static dynamic random access memory
  • Super dynamic random access memory

Question 87

Question
How many restrictions RAW hazards through memory are maintained?
Answer
  • 3
  • 4
  • 2

Question 88

Question
In Multilevel Caches “Misses per instruction” equals =
Answer
  • Misses in cache / number of instructions
  • Misses in cache / accesses to cache
  • Misses in cache / CPU memory accesses

Question 89

Question
How many possible Elements of Data Hazards?
Answer
  • 3
  • 6
  • 8

Question 90

Question
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” ?
Answer
  • The time from the reception of the response until the user begins to enter the next command
  • The time for the user to enter the command
  • The time between when the user enters the command and the complete response is displayed

Question 91

Question
Clock cycle time is -
Answer
  • Hardware technology and organization
  • Organization and instruction set architecture
  • Instruction set architecture and compiler technology

Question 92

Question
A virus classification by target includes the following categories. What is a File infector?
Answer
  • The key is stored with the virus
  • Far more sophisticated techniques are possible
  • A typical approach is as follows
  • Infects files that the operating system or shell consider to be executable

Question 93

Question
What is an ALAT?
Answer
  • Addition Long Accessibility Table
  • Allocated Link Address Table
  • Allowing List Address Table
  • Advanced Load Address Table

Question 94

Question
CPI is -
Answer
  • Hardware technology and organization
  • Organization and instruction set architecture
  • Instruction set architecture and compiler technology

Question 95

Question
What is SB?
Answer
  • Scaleboard
  • Scoreboard
  • Scorebased
  • Scalebit

Question 96

Question
At Critical Word First for miss penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
Answer
  • 0,1,2,3,4,5,6,7
  • 3,4,5,6,7,0,1,2

Question 97

Question
At Critical Word First for miss penalty chose correct sequence of Blocking Cache with critical word first “Order of fill”:
Answer
  • 0,1,2,3,4,5,6,7
  • 3,4,5,6,7,0,1,2

Question 98

Question
What is a RAID 0?
Answer
  • This organization was inspired by applying memory-style errorcorrecting codes to disks
  • it has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array
  • Also called mirroring or shadowing, there are two copies of every piece of data

Question 99

Question
What is a file?
Answer
  • It is the basic element of data
  • it is a collection of related fields that can be treated as a unit by some application program
  • it is a collection of related data
  • it is a collection of similar records

Question 100

Question
What is the reducing the miss penalty?
Answer
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Critical word first and merging write buffer
  • Small and simple first-level caches and way-prediction

Question 101

Question
Little’s Law and a series of definitions lead to several useful equations for “length server”-:
Answer
  • Average length of queue
  • Average number of tasks in service

Question 102

Question
At storage systems gray and Siewiorek classify faults what does mean “environmental faults”?
Answer
  • Fire, flood, earthquake, power failure and sabotage
  • Faults in software (usually) and hardware design (occasionally)
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Question 103

Question
How many types of dependencies do you know?
Answer
  • 3
  • 4
  • 5

Question 104

Question
How many major flavors in multiple-issue processors?
Answer
  • 3
  • 4
  • 5

Question 105

Question
Out-of-order control complexity MIPS R10000 which is not in control logic?
Answer
  • CLK
  • Address queue
  • Integer datapath
  • Free list

Question 106

Question
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches
Answer
  • Allow one instruction to branch multiple directions
  • Speculative operations that don’t cause exceptions

Question 107

Question
Infinite register renaming at the hardware model?
Answer
  • There are an infinite number of virtual registers available
  • Branch prediction is perfect, all conditional branches are predicted exactly

Question 108

Question
What is reducing hit time?
Answer
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Critical word first and merging write buffer
  • Small and simple first-level caches and way-prediction

Question 109

Question
Cycle time at memory latency is -
Answer
  • The time between when a read is requested and when the desired word arrives
  • the minimum time between unrelated requests to memory

Question 110

Question
Speculating on Exceptions “Prediction mechanism” is
Answer
  • None of them
  • exceptions are rare, so simply predicting no exceptions is very accurate
  • only write architecture state at commit point, so can throw away partially executed instructions after exception
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

Question 111

Question
How many main levels of cache memory?
Answer
  • 2
  • 8
  • 3
  • 6

Question 112

Question
What is the thread level parallelism -
Answer
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Question 113

Question
How many steps in instruction execution?
Answer
  • 4
  • 6
  • 3
  • 5

Question 114

Question
How many issue queue used in Centralized Superscalar 2 and exceptions?
Answer
  • 2
  • 4
  • 3
  • 1

Question 115

Question
What is a FL?
Answer
  • free leg
  • free list
  • free last
  • free launch

Question 116

Question
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time”-?
Answer
  • The time from the reception of the response until the user begins to enter the next command
  • the time between when the user enters the command and the complete response is displayed
  • the time for the user to enter the command

Question 117

Question
What is the “issue” in pipelining basics?
Answer
  • Decode instructions, check for data hazard
  • Decode instructions, check for control hazard
  • Decode instructions, check for structural hazard

Question 118

Question
Little’s Law and a series of definitions lead to several useful equations for “Length queue”
Answer
  • Average length of queue
  • Average number of tasks in service

Question 119

Question
Perfect jump prediction at The Hardware Model?
Answer
  • All jumps are perfectly predicted
  • All memory addresses are known exactly
  • Branch prediction is perfect

Question 120

Question
What is the term of dependability in SLOs?
Answer
  • Standard Level Offset
  • Standard Level Objectives

Question 121

Question
What is a FSB?
Answer
  • Finished store Buffer
  • Finished stack Buffer
  • Finished star Buffer
  • Finished stall Buffer

Question 122

Question
Out-of-order control complexity MIPS R10000 which is in control logic?
Answer
  • Data tags
  • Register name
  • Instruction cache
  • Data cache

Question 123

Question
Instruction count is –
Answer
  • Organization and instruction set architecture
  • Hardware technology and organization
  • Instruction set architecture and compiler technology

Question 124

Question
What is the Instruction Level Parallelism?
Answer
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Question 125

Question
What is the RLP?
Answer
  • Random Level Parallelism
  • Request Level Parallelism
  • Research Level Parallelism

Question 126

Question
In multilevel caches “Global miss rate” equals:
Answer
  • misses in cache / CPU memory accesses
  • misses in cache / accesses to cache
  • misses in cache / number of instructions

Question 127

Question
What does mean MSHR?
Answer
  • Miss Status Handling Register
  • Memory status handling register
  • mips status hardware prefetching
  • map status handling reload

Question 128

Question
What is the spatial locality?
Answer
  • Exploit by remembering the contents of recently accessed locations
  • Exploit by fetching blocks of data around recently accessed locations
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