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[Final Study] Unit 2 Pipelined CPU

Description

Unit 2 of UBC's CS313 course. Get some alcohol.
Zim Brightwood
Quiz by Zim Brightwood, updated more than 1 year ago
Zim Brightwood
Created by Zim Brightwood over 7 years ago
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Resource summary

Question 1

Question
Throughput is
Answer
  • the rate at which instructions leave the pipeline
  • total time it takes an instruction to be processed by a stage
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by the entire pipeline

Question 2

Question
Latency is
Answer
  • total time it takes an instruction to be processed by the entire pipeline
  • the rate at which instructions leave the pipeline
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by a stage

Question 3

Question
Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
Answer
  • Throughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
  • Throughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
  • Throughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up

Question 4

Question
Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
Answer
  • between each stage
  • after each stage
  • before each stage
  • inputs for that stage
  • outputs for that stage
  • inputs for the next stage
  • in parallel
  • sequentially

Question 5

Question
And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
Answer
  • in flight
  • executing
  • latent
  • active
  • retired
  • finished
  • complete
  • ready

Question 6

Question
The pipeline instructions are executed in order
Answer
  • True
  • False

Question 7

Question
Instruction-level parallelism exists between a pair of instructions if
Answer
  • their execution order does not matter
  • their execution order matters

Question 8

Question
The pipeline requires some parallelism
Answer
  • True
  • False

Question 9

Question
Dependencies exist if execution order doesn't matter
Answer
  • True
  • False

Question 10

Question
Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
Answer
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;
  • B write to a location read by A Example: b = a; a = 1;

Question 11

Question
Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
Answer
  • B write to visible location written by A Example: a = 1; a = 2;
  • B reads value written by A Example: a = 1; b = a;
  • B write to a location read by A Example: b = a; a = 1;

Question 12

Question
Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
Answer
  • B write to a location read by A Example: b = a; a = 1;
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;

Question 13

Question
[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
Answer
  • Expressing
  • Adding
  • Mechanizing
  • Conflating
  • Eating
  • Exploiting
  • Removing
  • Smelling
  • Tangential Execution

Question 14

Question
A pipeline hazard exists when
Answer
  • the processor's execution would violate a data or control dependency
  • the processor's execution would support a data or control dependency
  • the processor's execution would cause a data or control dependency
  • the processor's execution would execute a data or control dependency

Question 15

Question
We should detect pipeline hazards
Answer
  • True
  • False

Question 16

Question
Stalling is one way to handle pipeline hazards
Answer
  • True
  • False

Question 17

Question
A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle. A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.
Answer
  • pipeline stall
  • pipeline bubble
  • pipeline hazard
  • pipeline stage
  • pipeline overhead

Question 18

Question
The only data hazards in the Y86 Pipeline are causal hazards on register file
Answer
  • True
  • False

Question 19

Question
The only control hazards in the Y86 Pipeline are conditional jumps
Answer
  • True
  • False

Question 20

Question
To prevent a data hazard by stalling, we can
Answer
  • read registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
  • read registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
  • read registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired

Question 21

Question
How would we resolve a conditional jump control hazard by stalling?
Answer
  • stall fetch until jump exits execute
  • stall execute until jump exits decode
  • stall fetch and execute until jump exits decode
  • stall fetch, decode, and execute until jump exits memory
  • stall fetch, decode, execute, and memory until jump exits write back
  • just stall everything after fetch indefinitely and go finish off a bottle of wine in one go

Question 22

Question
How would we resolve a return control hazard by stalling?
Answer
  • stall fetch until return exits memory
  • stall decode until return exits memory
  • stall fetch and decode until return exits memory
  • stall fetch, decode, and execute until return exits memory
  • stall fetch, decode, execute, and memory until return exits memory
  • return to cpsc313 in the summer after you fail this midterm

Question 23

Question
Check all the statements that are true about the pipeline-control module
Answer
  • it's a hardware component separate from the 5 stages
  • examines values across every stage
  • decides whether stage should stall or bubble

Question 24

Question
Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
Answer
  • True
  • False

Question 25

Question
Where does data forwarding forward its data to?
Answer
  • D
  • W
  • M
  • E
  • F

Question 26

Question
Where does data forward forward its data from?
Answer
  • W - new value from memory or ALU
  • M - new value read from memory or from ALU
  • E - new value from ALU
  • D - new value from registers
  • F - new value from PC determined instruction

Question 27

Question
Which of these are data hazards?
Answer
  • register-register hazard
  • load-use hazard
  • register-memory hazard
  • memory-memory hazard
  • use-use hazard
  • load-load hazard

Question 28

Question
Which of these is a register-register hazard?
Answer
  • irmovl $1, %eax addl %eax, %ebx
  • irmovl $1, %ecx addl %eax, %ebx

Question 29

Question
How do we handle a register-register hazard with data forwarding?
Answer
  • forward to D from E, M, or W
  • forward to F from E, M, or W
  • stall one cycle, then forward to D from E, M, or W
  • stall one cycle, then forward to F from D, E, M, or W
  • stall one cycle, then forward to F from E, M, or W
  • forward to F from D, E, M, or W

Question 30

Question
Which of these is a load-use hazard?
Answer
  • mrmovl (esi), %eax addl %eax, %ebx
  • rmmovl %eax, (esi) addl %eax, %ebx

Question 31

Question
How would we handle a load-use hazard?
Answer
  • Stall use one cycle, forward to D from M or W
  • Stall use one cycle, forward to D from E or M
  • Stall use one cycle, forward to E from D, M, or W
  • Stall use one cycle, forward to E from M or W

Question 32

Question
Jump prediction is not suitable for resolving conditional-jump hazards
Answer
  • True
  • False

Question 33

Question
We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
Answer
  • E
  • D
  • M
  • W

Question 34

Question
valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
Answer
  • not taken
  • taken

Question 35

Question
When a mis-predicted jump is in M, what should we do?
Answer
  • shootdown D and E to prevent them from doing damage
  • shootdown F and D to prevent them from doing damage
  • shootdown M and W to prevent them from doing damage

Question 36

Question
The homework in this course is much too long
Answer
  • True
  • False

Question 37

Question
We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
Answer
  • True
  • False

Question 38

Question
We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
Answer
  • True
  • False

Question 39

Question
In regards to static jump prediction, what could the compiler know?
Answer
  • a jump's taken tendency
  • for loops, it can decide to use a continue condition or exit condition
  • for if statements it might be able to spot error tests
  • what it sees in the program text

Question 40

Question
The compiler cares about the ISA's jump predictions
Answer
  • True
  • False

Question 41

Question
How do we optimize handling the return hazard?
Answer
  • Keep a stack of return addresses for future use
  • Guess the return address based on the value in predPC
  • Guess the return address based on the value in PC
  • Guess the return address based on the valP in D

Question 42

Question
Y86 has indirect jumps
Answer
  • True
  • False

Question 43

Question
Indirect jumps are needed for polymorphic dispatch
Answer
  • True
  • False

Question 44

Question
CPI =
Answer
  • totalCycles / instructionRetiredCycles
  • instructionRetiredCycles / totalCycles

Question 45

Question
What are the tendencies of deeper pipelines?
Answer
  • reduce clock period
  • increase CPI
  • makes stalling harder to avoid

Question 46

Question
Which of these are attributes of super-scalar?
Answer
  • multiple pipelines that run in parallel
  • issue multiple instructions on each cycle
  • instructions execute in parallel and can even bypass each other
  • if I shut my eyes tight enough, will the midterm disappear?

Question 47

Question
What does hyper-threading consist of? (Only one of the following is correct)
Answer
  • OS loads multiple runnable threads into CPU, usually from the same process
  • CPU does fast switching between threads to hide memory latency

Question 48

Question
What is multi-core?
Answer
  • multiple CPUs per chip, each pipelined, super-scalar, etc
  • CPU's execute independent threads from possibly different processes

Question 49

Question
How could Mike do this to us?
Answer
  • Sadism
  • Also sadism
  • And sadism
  • All of the above
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