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Fragen in diesem Quiz (20)
1A callee-saved register should be saved before it is written to in a procedure
- ATrue
- BFalse
2A branch instruction
- AA. Sets the program counter to one of two possible values
- BB. Increases the program counter by a fixed amount
- CC. Sets the program counter to one of many possible values
- DD. Unconditionally sets the program counter to its operand
3A CPU register file is a small storage device that
- AA. Consists of a collection of word size registers
- BB. Houses a critical variable for the duration of the execution of a program
- CC. Records the results of periodic CPU diagnostics
- DD. Is automatically loaded when CPU instruction refers to a word of normal memory
4A memory leak is caused by a
- AC. None of these
- BB. Function that allocates a large amount of memory from the heap
- CD. Bug in the memory allocator that fails to free memory
- DA. Failure to free allocated memory
5A program cannot accidentally use another program's memory space and "crash" a computer that uses (see the img)
1- virtual memory address
2- program relocation
3- separate instruction and data caches- AB. 1 and 2
- BA. 1 only
- CC. 2
- DD. 1,2,3
6A program written directly in machine language (binary) would run faster than the same program written in assembly code and then assembled.
- AB. True
- BA. False
7Adding local variables is usually used to reduce what source of inefficiency?
- AA. unnecessary memory references
- BB. condition checking overhead
- CC. data dependencies
- DD. poor branch prediction
8Asserting a word line and asserting (to "high" voltage) a bit line writes a 1 to a DRAM cell)
- AA. False
- BB. True
9Assume a set-associative and a direct-mapped cache both have the same address size, same data capacity, and same number of index bits. This means
1. The direct-mapped cache has more tag bits
2. The direct-mapped cache has fewer tag bits
3. The direct-mapped cache has more block offset bits
4. The direct-mapped cache has fewer block offset bits- A1. The direct-mapped cache has more tag bits
- B2. The direct-mapped cache has fewer tag bits
- C3. The direct-mapped cache has more block offset bits
- D4. The direct-mapped cache has fewer block offset bits
10Assume x is the most positive signed integer. What is x + 1?
- AA. none of the above
- BB. +∞
- CC. -1
- DD. -x
11Assuming the standard IEEE-style bias, what is the smallest number of bits a float point number could have and represent the number −29/4 exactly?
- AA. 8
- BB. 4
- CC. 6
- DD. 12
12Buses are typically designed to transfer fixed-sized chunks of bytes known as
- AA. words
- BB. frames
- CC. records
- DD. pages
13. Capacity misses are typically discussed in connection with?
- AA. fully-associative caches
- BB. direct-mapped caches
- CC. set-associative caches
- DD. all of the above
14Check the following (listed in alphabetical order) in order of importance when optimizing code that operates on very large arrays: B = Body of loop optimization (function inlining, efficient math), C = Cache locality, O = big-O of algorithm used.
- AA. BCO
- BB. OBC
- CC. BOC
- DD. COB
15Compare the size of int and int*
- AA. each one of the above depends on the computer
- BB. int has fewer bits
- CC. int* has fewer bits
- DD. they have the same number of bits
16Compared to dynamic RAM (SRAM), dynamic RAM (DRAM) is
- AA. DRAM is cheaper than SRAM
- BB. DRAM is faster than SRAM
- CC. DRAM is more likely to be used for main memory than for on-chip caches
- DD. SRAM is more likely to be used for main memory than for on-chip caches
- EE. DRAM uses more transistors per bit than SRAM
- FF. DRAM uses a capacitor to store a value
- GG. Typically a computer has more DRAM than SRAM
17Compiling C into x86 assembly comprises translating each C statement into a single assembly instruction.
- AA. False
- BB. True
18Conflict misses are typically discussed in connection with?
- AA. direct-mapped caches
- BB. set-associative caches
- CC. fully-associative caches
- DD. all of the above
19CPE (cycles per element, also called cycles per execution or cycles per instruction in other sources). If we have code with 20 CPE and run it on a problem where my algorithm executes on 100 elements; I should expect the runtime to be:
- AA. 50-220 cycles
- BB. 0-50 cycles
- CC. 220-1100 cycles
- DD. 1100-2200 cycles
20Define the polarity of light sensor.
- AA. Long leg is plus, short is minus
- BB. Long leg is minus, short is plus.
- CC. It does not have a polarity.
- DD. None of the given.
Informationen
- Beschreibung
- Quiz am Ohne Titel, erstellt von Axakalov Beksultan am 12/05/2018.
- Autor
- Axakalov Beksultan
- Sprache
- English
- Aufrufe
- 3
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