Quiz
БАЗА 2 (Questions 91 - 153)
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Fragen in diesem Quiz (70)
1Flash memory is a type of -
- AElectronically Erasable Programmable Read-Only Memory
- BElectronically Extensible Programmable Re-Order Memory
- CElectronically Executable Programmable Reduce Memory
2What is a RT?
- ARename Table
- BRecall Table
- CRelocate Table
- DRemove Table
3What is the ARF?
- AArchitectural Register File
- BArchitecture Relocation File
- CArchitecture Reload File
- DArchitectural Read File
4How many functions at integrated instruction fetch units?
- A3
- B4
- C5
5What is the PMD in computer classes?
- APercentage map device
- BPersonal mobile device
- CPowerful markup distance
- DPeak maze development
6The second type of dependence is?
- AData dependence
- BName dependence
- CControl dependence
7How many elements presented at performance trends: bandwidth over latency?
- A4
- B5
- C3
8How many elements in trends of technology?
- A5
- B6
- C4
9What is the reducing the miss rate?
- AWhat is the reducing the miss rate?
- BPerformance optimization
- CCompiler optimization
- DTime optimization
10DDR is –
- ADouble data rate
- BDensity data rate
- CDynamic data rate
11Which distance of price has clusters/warehouse-scale computers?
- A100-100 000$
- B100 000-200 000 000$
- C5 000 -10 000 000$
12What is the MISD one of the categories of computers?
- AMultiple instructions streams, set data stream
- BMultiple instructions streams, single data stream
- CMultiple instruction stream, multiple data streams
13Main term of dependability is SLAs?
- AScale level approach
- BService level agreements
- CStandard level achievement
14Main term of dependability is SLOs?
- AStandart level offset
- BService level objectives
15At VLIW by “performance and loop iteration” which time is longer?
- ALoop unrolled
- BSoftware Pipelined
16What is an IQ?
- AIssue Queue
- BInternal Queue
- CInterrupt Queue
- DInstruction Queue
17What is a RISC computers?
- AReduced instruction set computer
- BResearch interconnect several computer
- CRational interruptible security computer
18The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
- A4
- B5
- C6
19What is the “opcode”?
- AOperand code
- BOptional code
- COperation code
20At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
21At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:
- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
22What is PRF?
- APipeline Register File
- BPhysical Register File
- CPure Register File
- DPending Register File
23What is FSB?
- AFinished Stack Buffer
- BFinished Store Buffer
- CFinished Stall Buffer
- DFinished Star Buffer
24Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?
- A3
- B4
- C2
25How many instructions used in Distributed Superscalar 2 and Exceptions?
- A1
- B2
- C3
- D4
26What is about Superscalar means “F-D-X-M-W”?
- AFetch, Decode, Instruct, Map, Write
- BFetch, Decode, Excite, Memory, Write
- CFetch, Decode, Except, Map, Writeback
- DFetch, Decode, Execute, Memory, Writeback
27 How many restrictions RAW hazards through memory are maintained?
- A3
- B4
- C2
28How many possible Elements of Data Hazards?
- A3
- B6
- C8
29A virus classification by target includes the following categories. What is a File infector?
- AThe key is stored with the virus
- BFar more sophisticated techniques are possible
- CA typical approach is as follows
- DInfects files that the operating system or shell consider to be executable
30What is an ALAT?
- AAddition Long Accessibility Table
- BAllocated Link Address Table
- CAllowing List Address Table
- DAdvanced Load Address Table
31CPI is -
- AHardware technology and organization
- BOrganization and instruction set architecture
- CInstruction set architecture and compiler technology
32What is SB?
- AScaleboard
- BScoreboard
- CScalebit
- DScorebased
33What is the ROB?
- AReorder buffer
- BRead only buffer
- CRelocate buffer
34SDRAM is -
- ASynchronous dynamic random access memory
- BStatic dynamic random access memory
- CSuper dynamic random access memory
35DRAM is -
- ADynamic random access memory
- BDual random access memory
- CDataram Random access memory
36What is a file?
- AIt is the basic element of data
- Bit is a collection of related fields that can be treated as a unit by some application program
- Cit is a collection of related data
- Dit is a collection of similar records
37How many major flavors in multiple-issue processors?
- A3
- B4
- C5
38 At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches
- AAllow one instruction to branch multiple directions
- BSpeculative operations that don’t cause exceptions
39Infinite register renaming at the hardware model?
- AThere are an infinite number of virtual registers available
- BBranch prediction is perfect, all conditional branches are predicted exactly
40What is reducing hit time?
- APipelined caches, multibanked caches, and nonblocking caches
- BCritical word first and merging write buffer
- CSmall and simple first-level caches and way-prediction
41How many main levels of cache memory?
- A2
- B8
- C3
- D6
42How many steps in instruction execution
- A4
- B6
- C3
- D5
43How many issue queue used in Centralized Superscalar 2 and exceptions?
- A2
- B4
- C3
- D1
44What is a FL?
- AFree leg
- Bfree list
- Cfree last
- Dfree launch
45What is a RISC computers?
- AResearch Interconnect Several Computer
- BRational Interruptible Security Computer
- CReduced Instruction Set Computer
46What is a Latency
- Ais time for a single
access – Main memory latency is usually >> than processor cycle time - Bis the number of
accesses per unit time – If m instructions are loads/stores, 1 + m memory
accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per
cycle - Cis amount of data that
can be in flight at the same time (Little’s Law)
- Ais time for a single
47What occurs at Intruction fetches when we speak about Common And
Predictable Memory Reference Patterns?- An loop iterations
- Bsubroutine call
- Cvector access
48 What occurs at Stack access when we speak about Common And Predictable
Memory Reference Patterns- Asubroutine call
- Bn loop iterations
- Cvector access
49What occurs at Data access when we speak about Common And Predictable
Memory Reference Patterns- Asubroutine call
- Bn loop iterations
- Cvector access
50Cache HIT:
- ANo Write Allocate,
No Write Allocate, - BWrite Through, Write
Back
- ANo Write Allocate,
51Cache MISS:
- ANo Write Allocate,
Write Allocate - BWrite Through, Write
Back
- ANo Write Allocate,
52Average Memory Access Time is equal:
- AHit Time * ( Miss Rate + Miss Penalty )
- BHit Time - ( Miss Rate + Miss Penalty )
- CHit Time / ( Miss Rate - Miss Penalty )
- DHit Time + ( Miss Rate * Miss Penalty )
53Algorithm for Cache HIT:
- AProcessor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
- BProcessor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- CProcessor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
54Algorithm for Cache MISS:
- AProcessor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
- BProcessor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
- CProcessor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
55The formula of “Iron Law” of Processor Performance:
- Atime/program = instruction/program * cycles/instruction * time/cycle
- Btime/program = instruction/program * cycles/instruction + time/cycle
- Ctime/program = instruction/program + cycles/instruction * time/cycle
56Structural Hazard:
- AAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- BAn instruction depends on a data value produced by an earlier instruction
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
57Data Hazard:
- AAn instruction depends on a data value produced by an earlier instruction
- BAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
- CWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
58Control Hazard:
- AWhether or not an instruction should be executed depends on a control decision made by an earlier instruction
- BAn instruction depends on a data value produced by an earlier instruction
- CAn instruction in the pipeline needs a resource being used by another instruction in the pipeline
59What is a Bandwidth:
- Aa is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis amount of data that can be in flight at the same time (Little’s Law)
60 What is a Bandwidth-Delay Product:
- Ais amount of data that can be in flight at the same time (Little’s Law)
- Bis time for a single access – Main memory latency is usually >> than processor cycle time
- Cis the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
61What is Computer Architecture?
- Ais the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
- Bis a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
- Cthe programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
62Least Recently Used (LRU):
- Acache state must be updated on every access
- BUsed in highly associative caches
- CFIFO with exception for most recently used block(s)
63Cache Hit –
- AWrite Through – write both cache and memory, generally higher traffic but simpler to design
- Bwrite cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
- CNo Write Allocate – only write to main memory
64Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
- AIf cache size is
doubled, miss rate usually drops by about √2 - BDirect-mapped cache of
size N has about the same miss rate as a two-way set- associative cache of size
N/2 - CNone of them
- AIf cache size is
65Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
- ADirect-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
- BIf cache size is doubled, miss rate usually drops by about √2
- CNone of them
66What does SRAM stands for?
- AStatic Random Access memory
- BSystem Random Access memory
- CShort Random Accessmemory
- DNone of them
67What does DRAM stands for?
- ADynamic Random Access memory
- BDual Random Access memory
- CDataram Random Access memory
68What is kernel process?
- AProvide at least two modes, indicating whether the running process is a user process or an operating system process
- BProvide at least five modes, indicating whether the running process is a user process or an operating system process
- CProvide a portion of the processor state that a user process can use but not write
- DNone of them
69Which one is NOT concerning to pitfall?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
70Which one is concerning to fallacy?
- APredicting cache performance of one program from another
- BSimulating enough instructions to get accurate performance measures of the memory hierarchy
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOver emphasizing memory bandwidth in DRAMs
Informationen
- Beschreibung
- PC Architecture Quiz am БАЗА 2 (Questions 91 - 153), erstellt von Csse 1502 am 23/05/2018.
- Autor
- Csse 1502
- Sprache
- English
- Aufrufe
- 37
- Schlagwörter
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