Quiz
CSA (Your Christmas Gift)
Fragen in diesem Quiz (49)
1Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:
- Aa system clock
- Ba system processor
- Ca clock processor
- Da processor
- Ea clock
2Typically all operations performed by a processor begin with the:
- Apulse of the clock
- Bpulse of the processor
- Cit begins by itself
- Dboth of clock and processor pulse
- Enone of the above
3The time between pulses called?
- Aclock speed
- Bclock rate
- Ccycle time
- Dclock cycle
- Ecycle rate
4Typically, clock signals are generated by a ______, which generates a constant signal wave while power is applied.
- Aquartz crystal
- Bcalcium crystal
- Czinc crystal
- Dmercury crystal
- Eradium crystal
5A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:
- AInstruction execution rate
- BInstruction execution cycle
- CInstruction execution time
- DInstruction execution period
- ENone of the above
6Average cycles per instruction of a program called:
- ACPU
- BClock cycle time
- CCPI
- DClock rate
- ECPE
7__ is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.
- AA benchmark suite
- BA performance suite
- CA IDE suite
- DA MIPS suite
- ENone of the above
8Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors
- ARichtig
- BFalsch
9SPEC Benchmarks, which evaluates the performance of World Wide Web (WWW) servers:
- ASPECjvm98
- BSPECjbb2000
- CSPECweb99
- DSPECmail2001
- Eall of the above
10SPEC Benchmarks, which intended to evaluate performance of the combined hardware and software aspects of the Java Virtual Machine (JVM) client platform:
- ASPECjvm98
- BSPECjbb2000
- CSPECweb99
- DSPECmail2001
- Eall of the above
11SPEC Benchmarks, which for evaluating server-side Java-based electronic commerce applications:
- ASPECjvm98
- BSPECjbb2000
- CSPECweb99
- DSPECmail2001
- Eall of the above
12SPEC Benchmarks, which designed to measure a system’s performance acting as a mail server
- ASPECjvm98
- BSPECjbb2000
- CSPECweb99
- DSPECmail2001
- Eall of the above
13ENIAC stands for:
- AElectronic Numerical Integrator and Computer
- BElectronic Nuclear Integrator and Computer
- CEncapsulation Numerical Integrator and Commerce
- DEncapsulation Numerical Integrator and Computer
- EElectronic Numerical Integer and Computer
14The general structure of the IAS computer:
- Amain memory
- Barithmetic and logic unit
- Ccontrol unit
- DInput/output equipment
- Eall of the above
15Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
16Specifies the address in memory of the word to be written from or read into the MBR
- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
17Contains the 8-bit opcode instruction being executed.
- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
18Employed to hold temporarily the right-hand instruction from a word in memory
- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
19Contains the address of the next instruction pair to be fetched from memory.
- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
20Transistor is a solid-state device, made from silicon
- ARichtig
- BFalsch
21The use of the _______ defines the second generation of computers.
- AVacuum tube
- BTransistor
- CSmall- and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
22The use of the _______ defines the first generation of computers.
- AVacuum tube
- BTransistor
- CSmall- and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
23The use of the ________ defines the third generation of computers.
- AVacuum tube
- BTransistor
- CSmall- and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
24The use of the _________ defines the fourth generation of computers.
- AVacuum tube
- BTransistor
- CSmall- and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
25The use of the _________ defines the fifth generation of computers.
- AVacuum tube
- BTransistor
- CSmall- and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
26Moore’s law: “The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic
- ARichtig
- BFalsch
27Moore’s law: “Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed”
- ARichtig
- BFalsch
28Moore’s law: “The computer becomes smaller, making it more convenient to place in a variety of environments”
- ARichtig
- BFalsch
29Moore’s law: “There is a reduction in power and cooling requirements”
- ARichtig
- BFalsch
30
Moore’s law: “The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections”- ARichtig
- BFalsch
31When Intel was developed its 4004, it is the first chip to contain all of the components of a CPU on a single chip, later known as Microprocessor
- A1973
- B1971
- C1972
- D1974
- E1970
32Processor can simultaneously work on multiple instructions. How this technique called?
- ABranch prediction
- BPipelining
- CData flow analysis
- DSpeculative execution
- ENone of the above
33The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next
- ABranch prediction
- BPipelining
- CData flow analysis
- DSpeculative execution
- ENone of the above
34The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
- ABranch prediction
- BPipelining
- CData flow analysis
- DSpeculative execution
- ENone of the above
35This enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed
- ABranch prediction
- BPipelining
- CData flow analysis
- DNone of the above
- ESpeculative execution
36The “natural” unit of organization of memory
- AWord
- BAddressable units
- CUnit of transfer
- DSequential access
- EDirect access
37For main memory, this is the number of bits read out of or written into memory at a time
- AWord
- BAddressable units
- CUnit of transfer
- DSequential access
- EDirect access
38Memory is organized into units of data, called records; access must be made in a specific linear sequence
- AWord
- BAddressable units
- CUnit of transfer
- DSequential access
- EDirect access
39For random-access memory, this is the time it takes to perform a read or write operation
- AAccess time
- BMemory cycle time
- CTransfer rate
- DPerformance
- EAll of the above
40The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
- ARichtig
- BFalsch
41The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
- ARichtig
- BFalsch
42Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches
- ABus watching with write through
- BHardware transparency
- CNoncacheable memory
- DSoftware transparency
- ENone of the above
43Each cache controller monitors the address lines to detect write operations to memory by other bus masters
- ABus watching with write through
- BHardware transparency
- CNoncacheable memory
- DSoftware transparency
- ENone of the above
44Only a portion of main memory is shared by more than one processor, and this is designated as:
- ABus watching with write through
- BHardware transparency
- CNoncacheable memory
- DSoftware transparency
- ENone of the above
45Larger blocks increase the number of blocks that fit into a cache; because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched
- ARichtig
- BFalsch
46A state in which data requested for processing by a component or application is found in the cache memory
- Acache hit
- Bcache miss
- Ccache overwrites
- Dcache set
- Ecache access time
47The basic element of a semiconductor memory is:
- Amemory cell
- Bcache memory
- CRAM
- DDRAM
- ENone of the above
48RAID stands for
- ARandom Access Integral Disk
- BRedundant Access Integral Disk
- CRandom Array Independent Disk
- DRedundant Array Independent Disk
- ERedundant Access Independent Disk
49Data are recorded on and later retrieved from the disk via a conducting coil named the tail
- ARichtig
- BFalsch
Informationen
- Beschreibung
- God Philosophy Quiz am CSA (Your Christmas Gift), erstellt von хомяк убийца am 23/03/2019.
- Autor
- хомяк убийца
- Sprache
- English
- Aufrufe
- 323
- Schlagwörter
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