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Quiz von хомяк убийца, aktualisiert more than 1 year ago
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Frage 1
Frage
The main computer that stores the files that can be sent to computers that are
networked together is...?:
Antworten
-
Clip art
-
Mother board
-
Peripheral
-
File server
Frage 2
Frage
Addressing mode used in instruction: add r1, r2, r3 is?
Antworten
-
Register
-
Indirect
-
Base
-
Immediate
Frage 3
Frage
In generic microprocessor instruction time is…?
Antworten
-
Exactly same as machine cycle time
-
Shorter than machine cycle time
-
Larger than machine cycle time
-
Ten times machine cycle time
Frage 4
Frage
Hardware devices that are not part of the main computer system and are often added later to the system?
Antworten
-
Peripheral
-
Clip art
-
Highlight
-
Execute
Frage 5
Frage
Using a(n) _____ protocol, the sender and the receiver are synchronized by a
signal called a clock
Antworten
-
synchronous
-
asynchronous
-
analogue
-
block
Frage 6
Frage
The bandwidth of a(n) _____ signal is usually measured in bits per second.
Antworten
-
video
-
digital
-
satellite
-
analog
Frage 7
Frage
A communications _____ is a physical path or frequency for a signal
transmission.
Antworten
-
band
-
channel
-
protocol
-
bridge
Frage 8
Frage
Which of the following terms represents the transmission capacity of a
communications channel?
Antworten
-
Indexing
-
Frequency
-
Bandwidth
-
Resolution
Frage 9
Frage
How many parts of Memory Hierarchy?
Antworten
-
5
-
4
-
2
-
3
Frage 10
Frage
In Memory Hierarchy, at the Outboard storage which of the following are
included:
Antworten
-
Cache
-
Main memory
-
Magnetic tape
-
Magnetic disk
Frage 11
Frage
In Memory Hierarchy, at the Off-line storage which of the following are included:
Antworten
-
Cache
-
Magnetic disk
-
Magnetic tape
-
Main memory
Frage 12
Frage
In Memory Hierarchy, at the Inboard memory which of the following are
included:
Antworten
-
Main memory
-
Magnetic disk
-
Magnetic tape
-
Optical disk
Frage 13
Frage
Cache Design has these properties?
Antworten
-
Size, block size, mapping function, replacement algorithm, write policy
-
Size, search function, write function, read policy, vector algorithm
-
Size, mapping algorithm, vector function, write policy, replacement function
-
Size, blocking algorithm, search function, replacement vector, read policy
Frage 14
Frage
Three techniques are possible for I/O operations:
Antworten
-
Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
-
Object-oriented I/O, Design I/O, Usable I/O
-
Machine I/O, Architecture I/O, Hardware I/O
-
Control I/O, Status I/O, Transfer I/O
Frage 15
Frage
How many principles has Deadlock?
Antworten
-
3
-
5
-
2
-
6
Frage 16
Frage
Which of the following principles has Deadlock?
Antworten
-
Prevention, Avoidance, Detection
-
Execution, Association, Starvation
-
Exclusion, Avoidance, Starvation
-
Starvation, Detection, Exclusion
Frage 17
Frage
Much of the work in security and protection as it relates to operating systems
can be roughly grouped into four categories?
Antworten
-
Availability, confidentiality, data integrity, authenticity
-
Safety, accountability, reliability, density
-
Usability, integrity, confidentiality, reliability
-
Flexibility, availability, accountability, authenticity
Frage 18
Frage
The central themes of operating system design are all concerned with the
management of processes and threads?
Antworten
-
Multiprogramming, multiprocessing, distributed processing
-
Multitasking, multiprogramming, multithreading
-
Multiprocessing, uniprocessing, multitasking
-
Multithreading, distributed processing, uniprocessing
Frage 19
Frage
Can you solve the Dining Philosophers’ Problem using monitors?
Antworten
-
yes
-
no
Frage 20
Frage
Assembly line operation is also called as?
Antworten
-
Superscalar operation
-
pipelining process
-
Von-Neumann cycle
-
None of the mentioned
Frage 21
Frage
The CISC stands for?
Antworten
-
Computer Instruction Set Compliment
-
Complete Instruction Set Compliment
-
Computer Indexed Set Components
-
Complex Instruction Set Computer
Frage 22
Frage
The secondary effect that results from instruction scheduling in large code
segments is called ____?
Antworten
-
Aggressive instruction
-
Correlating predictors
-
Register predictors
-
Register pressure
Frage 23
Frage
How many instructions can be implemented in MIPS?
Antworten
-
2 clock cycles
-
3 clock cycles
-
4 clock cycles
-
5 clock cycles
Frage 24
Frage
What do you call the given statement as: “The number successful accesses to
memory stated as a fraction.”
Antworten
-
Hit rate
-
Miss rate
-
Success rate
-
Access rate5 clock cycles
Frage 25
Frage
Of the following, identify the memory usually written by the manufacturer.
Antworten
-
RAM
-
DRAM
-
ROM
-
Cache memory
Frage 26
Frage
The Sun micro systems processors usually follow _____ architecture
Antworten
-
CISC
-
ISA
-
ULTRA SPARC
-
RISC
Frage 27
Frage
The iconic feature of the RISC machine among the following are
Antworten
-
Reduced number of addressing modes
-
Increased memory size
-
Having a branch delay slot
-
All of the above
Frage 28
Frage
Pipe-lining is a unique feature of _
Antworten
-
RISC
-
СISC
-
IANA
-
ISA
Frage 29
Frage
Performance of a machine is determined by:
Antworten
-
Instruction count, Clock cycle time, Clock cycles per instruction
-
Instruction count, Clock cycle time, Correlating predictors
-
Clock cycle time, Correlating predictors, Aggressive instruction
-
Clock cycle time, Clock cycles per instruction, Correlating predictors
Frage 30
Frage
What do you call the given statement as for type of memory?: “High density, low
power, cheap, slow, need to be “refreshed” regularly”
Antworten
-
DRAM
-
SRAM
-
CISC
-
RAM
-
ROM
Frage 31
Frage
Definition of Block:
Antworten
-
minimum unit that is present or not present
-
location of block in memory
-
percentage of time item not found in upper level
-
memory closer to processor
-
time to access upper level
Frage 32
Frage
Definition of Block address:
Antworten
-
minimum unit that is present or not present
-
location of block in memory
-
percentage of time item not found in upper level
-
memory closer to processor
-
time to access upper level
Frage 33
Antworten
-
196
-
784
-
512
-
1024
Frage 34
Frage
What is the total number of writes that miss in the cache?
Antworten
-
588
-
196
-
25%
-
12,5%
Frage 35
Frage
What is the total number of writes that hit in the cache?
Antworten
-
588
-
784
-
12,5%
Frage 36
Frage
Suppose that we want to enhance the processor used for Web serving. The new
processor is 10 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Antworten
-
≈ 1.86
-
≈ 1.96
-
≈ 1.56
-
1.30
Frage 37
Frage
Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Antworten
-
≈ 1.25
-
≈ 1.96
-
≈ 1.56
-
1.30
Frage 38
Frage
Suppose that we want to enhance the processor used for Web serving. The new
processor is 5 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 50% of the time and is waiting for I/O 50% of the time, what is the
overall speedup gained by incorporating the enhancement?
Antworten
-
≈ 1.86
-
≈ 1.96
-
≈ 1,67
-
1.30
Frage 39
Frage
Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 30% of the time and is waiting for I/O 70% of the time, what is the overall speedup gained by incorporating the enhancement?
Antworten
-
≈ 1.86
-
≈ 1.18
-
≈ 1.56
Frage 40
Frage
What is a RISC?
Antworten
-
Reduced Instruction Set Computer
-
Rational Interruptible Security Computer
-
Research Interconnect Several Computer
Frage 41
Frage
When single-processor performance improvement has dropped?
Antworten
-
2003
-
2004
-
2002
Frage 42
Frage
How much in percentage single-processor performance improvement has dropped to less than?
Antworten
-
22
-
11
-
33
Frage 43
Frage
What is the RLP?
Antworten
-
Research Level Parallelism
-
Random Level Parallelism
-
Request Level Parallelism
Frage 44
Frage
How many classes of computers classified?
Antworten
-
7
-
3
-
5
Frage 45
Frage
Which distance of price has Clusters/warehouse-scale computers?
Antworten
-
100 000 - 200 000 000 $
-
5 000 – 10 000 000 $
-
100 – 100 000 $
Frage 46
Frage
What is the PMD in computer classes?
Antworten
-
Percentage map device
-
Powerful markup distance
-
Peak maze development
-
Personal mobile device
Frage 47
Frage
The Application of Brokerage operations how many cost of downtime per hour?
Antworten
-
8 870 000 $
-
6 450 000 $
-
7 550 000 $
Frage 48
Frage
What is the Vector Architectures and Graphic Processor Units (GPUs) -
Antworten
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Frage 49
Frage
What is the Thread Level Parallelism -
Antworten
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Frage 50
Frage
What is the Request Level Parallelism:
Antworten
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Frage 51
Frage
What is the Instruction Level Parallelism:
Antworten
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Frage 52
Frage
What is the MISD one of the categories of computers?
Antworten
-
Multiple Instructions Streams, Single Data Stream
-
Multiple Instruction Streams, Multiple Data Streams
-
Multiple Instruction Streams, Set Data Stream
Frage 53
Frage
How many elements in Trends of Technology?
Antworten
-
3
-
4
-
5
Frage 54
Frage
How many elements of the Instruction Set Architecture (ISA):
Antworten
-
5
-
6
-
7
Frage 55
Frage
What is a ARF:
Antworten
-
Architectural Register File
-
Architecture Relocation File
-
Architecture Reload File
-
Architectural Read File
Frage 56
Frage
What is a ROB?
Antworten
-
Reorder Buffer
-
Read Only Buffer
-
Reload Buffer
-
Recall Buffer
Frage 57
Frage
What is a FSB?
Antworten
-
Finished Store Buffer
-
Finished Stack Buffer
-
Finished Stall Buffer
-
Finished Star Buffer
Frage 58
Frage
What is a PRF?
Antworten
-
Physical Register File
-
Pending Register File
-
Pipeline Register File
-
Pure Register File
Frage 59
Frage
What is a SB?
Antworten
-
Scoreboard
-
Scorebased
-
Scaleboard
-
Scalebit
Frage 60
Frage
How many stages used in Superscalar (Pipeline)?
Antworten
-
5
-
4
-
6
Frage 61
Frage
What is about Superscalar means “F-D-X-M-W”?
Antworten
-
Fetch, Decode, Execute, Memory, Writeback
-
Fetch, Decode, Instruct, Map, Write
-
Fetch, Decode, Excite, Memory, Write
-
Fetch, Decode, Except, Map, Writeback
Frage 62
Frage
Speculating on Exceptions “Prediction mechanism” is -
Antworten
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
none
Frage 63
Frage
Speculating on Exceptions “Check prediction mechanism” is -
Antworten
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
The way in which an object is accessed by a subject
-
none
Frage 64
Frage
Speculating on Exceptions “Recovery mechanism” is -
Antworten
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
An entity capable of accessing objects
-
none
Frage 65
Frage
What is a RT?
Antworten
-
Rename Table
-
Recall Table
-
Relocate Table
-
Remove Table
Frage 66
Frage
What is a FL?
Antworten
-
Free List
-
Free Last
-
Free Leg
-
Free Launch
Frage 67
Frage
What is an IQ?
Antworten
-
Issue Queue
-
Internal Queue
-
Interrupt Queue
-
Instruction Queue
Frage 68
Frage
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Antworten
-
Width and Lifetime
-
Width and Height
-
Time and Cycle
-
Length and Addition
Frage 69
Frage
Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?
Antworten
-
Register name
-
Instruction cache
-
Data tags
-
Data cache
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