Quiz
Test4
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1What are the advantages of SIMD parallelism?
- AIt matches well with matrix-oriented computations.
- BIt is more energy efficient than MIMD (multiple instruction multiple data) architectures.
- CIt allows programmers to continue thinking sequentially yet achieve parallel speedup by having parallel data operations
- DIt can attain more scalable parallelism than MIMD.
2What are the main forms of SIMD parallelism in modern computer architecture?
- AGraphics Processing Units (GPUs) that work as special purpose accelerators of CPUs.
- BMultimdedia extensions that optionally work on wider registers than those used in normal operating mode.
- CMulti-core processors that support multiple concurrent CPU cores per processor.
- DTraditional vector processors that operate on specialized long vector register files
3Which of the following summarize how the traditional vector architecture work?
- AVector loads and stores are deeply pipelined, with long memory latency triggered only once per vector load or store.
- BVector register files act as compiler-controlled buffers, both to hide memory latency and to leverage memory bandwidth.
- CEach instruction works on vectors of data and perform register-register operations on independent data elements.
- DIt does not support scalar-only operations.
- EIt grabs data elements scattered about memory and places them into large sequential register files
4What are The primary components of the instruction set architecture of RV64V?
- AThe type and width of each operand are determined by configuring each vector register rather than being supplied by the instruction.
- BScalar functional units to support scalar-only operations.
- CVector load/store units, each fully pipelined and loads or stores a vector to or from memory
- DScalar registers, serving to provide data to the vector functional units and to compute addresses to pass to the vector load/store unit.
- EVector registers, each holding a single vector and providing enough ports to feed all the vector functional units.
5Which of the following does NOT summarize how dynamic register typing work?
- AConversions between different size operands can be implicit depending on the configuration of the registers.
- BIt enables large vector registers, which implies slow context switch time.
- CIt allows programs to disable unused vector registers while allowing enabled vector registers to be allocated all the available vector memory.
- DThe type and width of each operand are determined by configuring each vector register.
- EAll vector instructions support operands being both vectors or one of them being vectors.
6Which of the following Is NOT a main factor that determines the success of vector architectures?
- AThe compiler support for developers to eaisly communicate how to vectorize their code.
- BThe ability of the compiler to automatically vectorize operations in user programs.
- CThe structure of user applications in terms of the amount of vector parallelism available
- DThe ability of the hardware to support an important domain of applications in a balanced efficient fashion.
7Complete the following instructions to correctly compute Z = X + Y, where Z,X,Y are vectors.
vsetdcfg [blank_start]4[blank_end] *FP64
vld v0, Rx
vld v1, Ry
vadd v2, v0, v1
vst [blank_start]v1[blank_end], Rz
vdisable- A4
- Bv1
8Which of the following explains the logistics for using predicate registers?
- AUsing predicate registers allows conditional vector instructions to be evaluated as efficiently as non-conditional ones.
- BIt provides vector-mask control, by using predicate (boolean) registers to hold the mask and provide conditional execution of each element operation in a vector instruction.
- CWhen the predicate register is set, all following vector instructions operate only on the vector elements whose corresponding entries in the predicate register are true.
- DPredicate registers are configured and can be disabled.
9Which of the following explain the logistics for Using independent memory banks for Vector Load/Store units?
- AThe initiation rate for load/store vector units may be slow because memory bank stalls can reduce effective throughput.
- BSimilar to using multiple memory banks to handle interleaving of memory addresses, it divides memory into a number of modules such that successive words in the address space are placed in a different module.
- CSpreading accesses across multiple independent memory banks usually delivers the better performance.
- DHaving independent memory banks is useful for vector loads or stores that access distinct rows or columns of data.
10Which of the following explain the logistics for using the stride register?
- ASupport for nonunit strides is slower than unit stride accesses when the stride causes regular conflicts in memory banks.
- Bhe vector stride, like the vector starting address, can be put in a general-purpose register.
- CIt allows a vector processor to handle nonunit strides using only vector load and vector store operations with stride capability.
- DIt supports the gathering of non-adjacent elements in memory into a single vector register.
11Which of the following explain the logistics for the Gather-Scatter optimization?
- AA gather operation takes an index vector, fetches elements by adding a base address to the offsets given in the index vector, and places the elements in dense vector register.
- BIt uses index vectors to support moving between a compressed representation (i.e., zeros are not included) and normal representation (i.e., the zeros are included) of a sparse matrix.
- CIt allows code with sparse matrices to run in vector mode, with similar efficiencies as that of dense matrix operations.
- DA scatter operation store values in a dense vector register to an expanded form in memory by using the same index vector.
12What are the main differences between SIMD Instruction Set Extensions for multimedia and the ISA of the vector architecture?
- ASIMD extensions cost little to add and are easy to implement.
- BSIMD extensions have no vector length register, no strided or gather/scatter data transfer instructions, and no mask registers.
- CIt is easier for developers to write code in SIMD extensions.
- DSIMD Multimedia Extensions target narrower data types than those in the 32-bit processors.
13for (i=0;i<n; i=i+1)
A[K] = A[K[i]] + C[M[i]];
Answer:
vsetdcfg [blank_start]4*FP64[blank_end] # enable 64b FP vector registers
vld v0, x7 # Load K[]
[blank_start]vldi[blank_end] v1, x5, v0 # Load A[K[]]
vld v2, x28 # Load M[]
[blank_start]vldi[blank_end] v3, x6, v2 # Load C[M[]]
vadd v1, v1, v3 # Add them
[blank_start]vsti[blank_end] v1, x5, v0) # Store A[K[]]
vdisable # Disable vector registers- A4*FP64
- Bvldi
- Cvldi
- Dvsti
14Which of the following is NOT a main factor that determines the execution time of vector operations?
- AData dependences among operations.
- BStructural hazards among the operations
- CThe vector length and the initiation rate of each vector register.
- DE. The memory load/store lantency
- EThe number of parallel pipelines (or lanes) available in each vector functional unit.
15Which of the following does NOT correctly define the concept of convoy?
- AThe instructions in a convoy must not contain any structural hazards.
- BIt refers to the set of vector instructions that could potentially execute together.
- CA convoy of instructions always complete execution before other instructions not in the convoy.
16Which of the following does NOT correctly summarize the concept of a chime?
- AIt ignores processor-specific overhead that are dependent on vector length.
- BIt is the unit of time taken to execute one convoy.
- CIt is used to estimate the number of operations contained in a convoy.
- DA vector sequence that consists of m convoys executes in m chimes;
- EIt is a better approximation for long vectors than for short ones.
17Which of the following does NOT correctly define the concept of chaining?
- AIt flexibly allows a vector instruction to chain to any other active vector instruction unless a structural hazard is generated.
- BIt allows a vector operation to start as soon as the individual elements of its operands become available
- CIt forwards the results of one vector functional unit immediately to the next one without delay.
- DIt works by allowing multiple functional units to read and write arbitrary vector register at the same time.
- EIt is used to support instruction sequences with read-after-write dependency hazards in the same convoy.
18Which of the following explains the logistics of the architectural optimization by using multiple lanes?
- AAdding multiple lanes can improve vector performance while requiring little increase in control complexity and no changes in existing machine code.
- BEach lane has its own local arithmetic pipelines and can complete operations without communicating with other lanes.
- CEach lane contains the 0th element of all vector registers and one execution pipeline from each vector functional unit.
- DEach vector functional unit executes vector instructions one element group per cycle using multiple pipelines, one per lane.
19Which of the following are correct regarding the logistics of using Vector-Length Registers?
- AThe value in the vector-length register cannot be greater than the maximum vector length (mvl)
- BEach vector processor has a maximum vector length for its operands. The length, however, may not match the amount of SIMD parallelism available in real code.
- CThe value in the vector-length register can be greater than the maximum vector length (mvl)
- DThe vector-length register (vl) is used to dynamically control the length of any vector operation.
- EIn a real program, the length of a vector operation is often unknown at compile time.
20Show how the following code sequence lays out in convoys, assuming a single copy of each vector functional unit.
I0: vld v0,x5 # Load vector X
I1: vmul v1,v0,f0 # Vector-scalar mult
I2: vld v2,x6 # Load vector Y
I3: vadd v3,v1,v2 # Vector-vector add # Store the sum
I4: vst v3,x6 # Store the sum
Answer:
Convoy1: I0 and I1
Convoy2: [blank_start]I2 and I3[blank_end]
Convoy3: [blank_start]I4[blank_end]- AI4
- BI2 and I3
21Which of the following is NOT part of the main NVidia's CUDA programming model?
- ADifferent Thread Blocks cannot communicate directly, although they can coordinate using atomic memory operations in global memory
- BIt executes a block of threads (called a Thread Block) in the SIMD fashion.
- CTo simplify scheduling by the hardware, thread Blocks are asynchronous and can execute in any order.
- DIt explores data parallelism through single instruction, multiple thread (SIMT) programming.
- EIt relies on multiple layers of hardware-managed cache to buffer the data.
- FIt relies on multi-threading to hide the memory latency within a single processor.
22Which of the following is not a level of parallelism supported by a GPU?
- ASIMD instructions (typically 32 wide) within each thread;
- BSIMD lanes, which are parallel function units inside the processor.
- CSIMD Threads within a SIMD Processor;
- DA large number of registers in the processor that can be divided among the threa
- EThread Blocks, which consist of bodies of vectorized loops, are scheduled to multithreaded SIMD Processors;
23Which of the following is NOT correct about GPU registers?
- AEach thread is dynamically allocated a set of the physical registers when it is created
- BAll registers allocated to a thread are freed when the SIMD Thread exits.
- CThe hardware decides and records where the registers for each Thread Block are in the large register file.
- DDifferent thread blocks may use different numbers of registers per thread.
- EDifferent threads in the same thread block may use different numbers of registers.
24Which of the following is NOT correct about the PTX (Parallel Thread Execution) instruction set of GPUs?
- ACompiler must calculate places where branches diverge and places where diverged paths could converge.
- BIt describes operations on a single CUDA Thread and often maps one-to-one with hardware instructions.
- CHardware must calculate places where branches diverge and places where diverged paths could converge.
- DOne PTX instruction can expand to many machine instructions, and vice versa.
- EPTX uses an unlimited number of write-once registers and the compiler must run a register allocation procedure to map them to a fixed number of read-write hardware registers.
25Which of the following is NOT correct about specifying control flow in PTX?
- AAll instructions can be predicated by 1-bit predicate registers, set by a predicate instruction (setp).
- BA different instruction is reserved for synchronizing across thread blocks.
- CIt includes Instructions for functions call, function return, thread exit, branch, and thread barrier synchronization.
- DSynchronization is allowed for threads inside a single Thread Block (bar.sync) only.
26Which of the following is NOT correct about supporting data transfers in GPU?
- ADeveloper is responsible for informing the hardware how to perform the data transfer efficiently
- BOnly a single mode of data transfer, gather-scatter, is supported.
- CTo attain good performance in data transfer, GPU programmer must ensure adjacent CUDA Threads access nearby addresses at the same time so that they can be coalesced into cache blocks.
- DSpecial Address Coalescing hardware is used to automatically rerecognize and optimize when the SIMD Lanes within a thread are collectively issuing sequential addresses.
27Which of the following is NOT correct about control divergence in GPU?
- APTX assembler typically optimizes a simple IF-THEN-ELSE to predicated GPU instructions without branch. These instructions operate at 50% GPU efficiency or less.
- BGPU hardware provides per-lane support for conditional branches.
- CGPU hardware provides each SIMD Thread with its own stack and per-lane predication (1-bit register).
- DThe PTX assembler analyzes the PTX branch graph and optimizes it to GPU hardware instruction sequence.
- EHardware uses internal masks, a branch synchronization stack, and instruction markers to manage diverged branches.
- FDiverged control flow is translated to a mixture of predication and branch instructions that use the per-thread stack.
28Translate the following C code to RV64V
for(i=0;i<64; i=i+1)
if (X!= 0)
X[i] = X[i] – Y[i];
vsetdcfg [blank_start]2*FP64[blank_end] # Enable 64b FP vector regs
vsetpcfg [blank_start]1[blank_end] # Enable predicate register
vld v0,x5 # Load vector X into v0
vld v1,x6 # Load vector Y into v1
fmv.d.x f0,x0 # Put (FP) zero into f0
[blank_start]vpeq[blank_end] p0,v0,f0 # Set p0(i) to 1 if v0(i)!=f0
vsub v0,v0,v1 # Subtract under vector mask
vst v0,x5 # Store the result in X
vdisable # Disable vector register
vpdisable # Disable predicate registers
- A2*FP64
- B1
- Cvpeq
Informationen
- Beschreibung
- Quiz am Test4, erstellt von Tyler Young am 08/05/2021.
- Autor
- Tyler Young
- Sprache
- English
- Aufrufe
- 4
- Verlauf
- Erstellt am 8 Mai 2021 · aktualisiert am 10 Mai 2021
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