Kopieren und bearbeiten

[Final Study] Unit 2 Pipelined CPU

Beschreibung

Unit 2 of UBC's CS313 course. Get some alcohol.
Zim Brightwood
Quiz von Zim Brightwood, aktualisiert more than 1 year ago
Zim Brightwood
Erstellt von Zim Brightwood vor mehr als 7 Jahre
48
0
0

Zusammenfassung der Ressource

Frage 1

Frage
Throughput is
Antworten
  • the rate at which instructions leave the pipeline
  • total time it takes an instruction to be processed by a stage
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by the entire pipeline

Frage 2

Frage
Latency is
Antworten
  • total time it takes an instruction to be processed by the entire pipeline
  • the rate at which instructions leave the pipeline
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by a stage

Frage 3

Frage
Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
Antworten
  • Throughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
  • Throughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
  • Throughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up

Frage 4

Frage
Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
Antworten
  • between each stage
  • after each stage
  • before each stage
  • inputs for that stage
  • outputs for that stage
  • inputs for the next stage
  • in parallel
  • sequentially

Frage 5

Frage
And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
Antworten
  • in flight
  • executing
  • latent
  • active
  • retired
  • finished
  • complete
  • ready

Frage 6

Frage
The pipeline instructions are executed in order
Antworten
  • True
  • False

Frage 7

Frage
Instruction-level parallelism exists between a pair of instructions if
Antworten
  • their execution order does not matter
  • their execution order matters

Frage 8

Frage
The pipeline requires some parallelism
Antworten
  • True
  • False

Frage 9

Frage
Dependencies exist if execution order doesn't matter
Antworten
  • True
  • False

Frage 10

Frage
Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
Antworten
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;
  • B write to a location read by A Example: b = a; a = 1;

Frage 11

Frage
Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
Antworten
  • B write to visible location written by A Example: a = 1; a = 2;
  • B reads value written by A Example: a = 1; b = a;
  • B write to a location read by A Example: b = a; a = 1;

Frage 12

Frage
Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
Antworten
  • B write to a location read by A Example: b = a; a = 1;
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;

Frage 13

Frage
[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
Antworten
  • Expressing
  • Adding
  • Mechanizing
  • Conflating
  • Eating
  • Exploiting
  • Removing
  • Smelling
  • Tangential Execution

Frage 14

Frage
A pipeline hazard exists when
Antworten
  • the processor's execution would violate a data or control dependency
  • the processor's execution would support a data or control dependency
  • the processor's execution would cause a data or control dependency
  • the processor's execution would execute a data or control dependency

Frage 15

Frage
We should detect pipeline hazards
Antworten
  • True
  • False

Frage 16

Frage
Stalling is one way to handle pipeline hazards
Antworten
  • True
  • False

Frage 17

Frage
A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle. A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.
Antworten
  • pipeline stall
  • pipeline bubble
  • pipeline hazard
  • pipeline stage
  • pipeline overhead

Frage 18

Frage
The only data hazards in the Y86 Pipeline are causal hazards on register file
Antworten
  • True
  • False

Frage 19

Frage
The only control hazards in the Y86 Pipeline are conditional jumps
Antworten
  • True
  • False

Frage 20

Frage
To prevent a data hazard by stalling, we can
Antworten
  • read registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
  • read registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
  • read registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired

Frage 21

Frage
How would we resolve a conditional jump control hazard by stalling?
Antworten
  • stall fetch until jump exits execute
  • stall execute until jump exits decode
  • stall fetch and execute until jump exits decode
  • stall fetch, decode, and execute until jump exits memory
  • stall fetch, decode, execute, and memory until jump exits write back
  • just stall everything after fetch indefinitely and go finish off a bottle of wine in one go

Frage 22

Frage
How would we resolve a return control hazard by stalling?
Antworten
  • stall fetch until return exits memory
  • stall decode until return exits memory
  • stall fetch and decode until return exits memory
  • stall fetch, decode, and execute until return exits memory
  • stall fetch, decode, execute, and memory until return exits memory
  • return to cpsc313 in the summer after you fail this midterm

Frage 23

Frage
Check all the statements that are true about the pipeline-control module
Antworten
  • it's a hardware component separate from the 5 stages
  • examines values across every stage
  • decides whether stage should stall or bubble

Frage 24

Frage
Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
Antworten
  • True
  • False

Frage 25

Frage
Where does data forwarding forward its data to?
Antworten
  • D
  • W
  • M
  • E
  • F

Frage 26

Frage
Where does data forward forward its data from?
Antworten
  • W - new value from memory or ALU
  • M - new value read from memory or from ALU
  • E - new value from ALU
  • D - new value from registers
  • F - new value from PC determined instruction

Frage 27

Frage
Which of these are data hazards?
Antworten
  • register-register hazard
  • load-use hazard
  • register-memory hazard
  • memory-memory hazard
  • use-use hazard
  • load-load hazard

Frage 28

Frage
Which of these is a register-register hazard?
Antworten
  • irmovl $1, %eax addl %eax, %ebx
  • irmovl $1, %ecx addl %eax, %ebx

Frage 29

Frage
How do we handle a register-register hazard with data forwarding?
Antworten
  • forward to D from E, M, or W
  • forward to F from E, M, or W
  • stall one cycle, then forward to D from E, M, or W
  • stall one cycle, then forward to F from D, E, M, or W
  • stall one cycle, then forward to F from E, M, or W
  • forward to F from D, E, M, or W

Frage 30

Frage
Which of these is a load-use hazard?
Antworten
  • mrmovl (esi), %eax addl %eax, %ebx
  • rmmovl %eax, (esi) addl %eax, %ebx

Frage 31

Frage
How would we handle a load-use hazard?
Antworten
  • Stall use one cycle, forward to D from M or W
  • Stall use one cycle, forward to D from E or M
  • Stall use one cycle, forward to E from D, M, or W
  • Stall use one cycle, forward to E from M or W

Frage 32

Frage
Jump prediction is not suitable for resolving conditional-jump hazards
Antworten
  • True
  • False

Frage 33

Frage
We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
Antworten
  • E
  • D
  • M
  • W

Frage 34

Frage
valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
Antworten
  • not taken
  • taken

Frage 35

Frage
When a mis-predicted jump is in M, what should we do?
Antworten
  • shootdown D and E to prevent them from doing damage
  • shootdown F and D to prevent them from doing damage
  • shootdown M and W to prevent them from doing damage

Frage 36

Frage
The homework in this course is much too long
Antworten
  • True
  • False

Frage 37

Frage
We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
Antworten
  • True
  • False

Frage 38

Frage
We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
Antworten
  • True
  • False

Frage 39

Frage
In regards to static jump prediction, what could the compiler know?
Antworten
  • a jump's taken tendency
  • for loops, it can decide to use a continue condition or exit condition
  • for if statements it might be able to spot error tests
  • what it sees in the program text

Frage 40

Frage
The compiler cares about the ISA's jump predictions
Antworten
  • True
  • False

Frage 41

Frage
How do we optimize handling the return hazard?
Antworten
  • Keep a stack of return addresses for future use
  • Guess the return address based on the value in predPC
  • Guess the return address based on the value in PC
  • Guess the return address based on the valP in D

Frage 42

Frage
Y86 has indirect jumps
Antworten
  • True
  • False

Frage 43

Frage
Indirect jumps are needed for polymorphic dispatch
Antworten
  • True
  • False

Frage 44

Frage
CPI =
Antworten
  • totalCycles / instructionRetiredCycles
  • instructionRetiredCycles / totalCycles

Frage 45

Frage
What are the tendencies of deeper pipelines?
Antworten
  • reduce clock period
  • increase CPI
  • makes stalling harder to avoid

Frage 46

Frage
Which of these are attributes of super-scalar?
Antworten
  • multiple pipelines that run in parallel
  • issue multiple instructions on each cycle
  • instructions execute in parallel and can even bypass each other
  • if I shut my eyes tight enough, will the midterm disappear?

Frage 47

Frage
What does hyper-threading consist of? (Only one of the following is correct)
Antworten
  • OS loads multiple runnable threads into CPU, usually from the same process
  • CPU does fast switching between threads to hide memory latency

Frage 48

Frage
What is multi-core?
Antworten
  • multiple CPUs per chip, each pipelined, super-scalar, etc
  • CPU's execute independent threads from possibly different processes

Frage 49

Frage
How could Mike do this to us?
Antworten
  • Sadism
  • Also sadism
  • And sadism
  • All of the above
Zusammenfassung anzeigen Zusammenfassung ausblenden

Möchten Sie mit GoConqr kostenlos Ihre eigenen Quiz erstellen? eigenen Mehr erfahren.

ähnlicher Inhalt

Computing Hardware - CPU and Memory
ollietablet123
SFDC App Builder 2
Parker Webb-Mitchell
Data Types
Jacob Sedore
Intake7 BIM L1
Stanley Chia
Software Processes
Nurul Aiman Abdu
Design Patterns
Erica Solum
CCNA Answers – CCNA Exam
Abdul Demir
Abstraction
Shannon Anderson-Rush
Spyware
Sam2
HTTPS explained with Carrier Pigeons
Shannon Anderson-Rush
Data Analytics
anelvr
Bibliothek durchsuchen