Quiz
[CPSC313 Final] Unit 2 Pipeline CPU
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Fragen in diesem Quiz (90)
1Throughput is
- Athe rate at which instructions leave the pipeline
- Btotal time it takes an instruction to be processed by a stage
- Cthe rate at which instructions move to the next register
- Dtotal time it takes an instruction to be processed by the entire pipeline
2Latency is
- Atotal time it takes an instruction to be processed by the entire pipeline
- Bthe rate at which instructions leave the pipeline
- Cthe rate at which instructions move to the next register
- Dtotal time it takes an instruction to be processed by a stage
3Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
- AThroughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
- BThroughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
- CThroughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up
4Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
- Abetween each stage
- Bafter each stage
- Cbefore each stage
- Dinputs for that stage
- Eoutputs for that stage
- Finputs for the next stage
- Gin parallel
- Hsequentially
5And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
- Ain flight
- Bexecuting
- Clatent
- Dactive
- Eretired
- Ffinished
- Gcomplete
- Hready
6The pipeline instructions are executed in order
- ARichtig
- BFalsch
7Instruction-level parallelism exists between a pair of instructions if
- Atheir execution order does not matter
- Btheir execution order matters
8The pipeline requires some parallelism
- ARichtig
- BFalsch
9Dependencies exist if execution order doesn't matter
- ARichtig
- BFalsch
10Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
- AB reads value written by A
Example:
a = 1;
b = a; - BB write to visible location written by A
Example:
a = 1;
a = 2; - CB write to a location read by A
Example:
b = a;
a = 1;
- AB reads value written by A
11Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
- AB write to visible location written by A
Example:
a = 1;
a = 2; - BB reads value written by A
Example:
a = 1;
b = a; - CB write to a location read by A
Example:
b = a;
a = 1;
- AB write to visible location written by A
12Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
- AB write to a location read by A
Example:
b = a;
a = 1; - BB reads value written by A
Example:
a = 1;
b = a; - CB write to visible location written by A
Example:
a = 1;
a = 2;
- AB write to a location read by A
13[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
- AExpressing
- BAdding
- CMechanizing
- DConflating
- EEating
- FExploiting
- GRemoving
- HSmelling
- ITangential Execution
14A pipeline hazard exists when
- Athe processor's execution would violate a data or control dependency
- Bthe processor's execution would support a data or control dependency
- Cthe processor's execution would cause a data or control dependency
- Dthe processor's execution would execute a data or control dependency
15We should detect pipeline hazards
- ARichtig
- BFalsch
16Stalling is one way to handle pipeline hazards
- ARichtig
- BFalsch
17A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle.
A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.- Apipeline stall
- Bpipeline bubble
- Cpipeline hazard
- Dpipeline stage
- Epipeline overhead
18The only data hazards in the Y86 Pipeline are causal hazards on register file
- ARichtig
- BFalsch
19The only control hazards in the Y86 Pipeline are conditional jumps
- ARichtig
- BFalsch
20To prevent a data hazard by stalling, we can
- Aread registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
- Bread registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
- Cread registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired
21How would we resolve a conditional jump control hazard by stalling?
- Astall fetch until jump exits execute
- Bstall execute until jump exits decode
- Cstall fetch and execute until jump exits decode
- Dstall fetch, decode, and execute until jump exits memory
- Estall fetch, decode, execute, and memory until jump exits write back
- Fjust stall everything after fetch indefinitely and go finish off a bottle of wine in one go
22How would we resolve a return control hazard by stalling?
- Astall fetch until return exits memory
- Bstall decode until return exits memory
- Cstall fetch and decode until return exits memory
- Dstall fetch, decode, and execute until return exits memory
- Estall fetch, decode, execute, and memory until return exits memory
- Freturn to cpsc313 in the summer after you fail this midterm
23Check all the statements that are true about the pipeline-control module
- Ait's a hardware component separate from the 5 stages
- Bexamines values across every stage
- Cdecides whether stage should stall or bubble
24 Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
- ARichtig
- BFalsch
25Where does data forwarding forward its data to?
- AD
- BW
- CM
- DE
- EF
26Where does data forward forward its data from?
- AW - new value from memory or ALU
- BM - new value read from memory or from ALU
- CE - new value from ALU
- DD - new value from registers
- EF - new value from PC determined instruction
27Which of these are data hazards?
- Aregister-register hazard
- Bload-use hazard
- Cregister-memory hazard
- Dmemory-memory hazard
- Euse-use hazard
- Fload-load hazard
28Which of these is a register-register hazard?
- Airmovl $1, %eax
addl %eax, %ebx - Birmovl $1, %ecx
addl %eax, %ebx
- Airmovl $1, %eax
29How do we handle a register-register hazard with data forwarding?
- Aforward to D from E, M, or W
- Bforward to F from E, M, or W
- Cstall one cycle, then forward to D from E, M, or W
- Dstall one cycle, then forward to F from D, E, M, or W
- Estall one cycle, then forward to F from E, M, or W
- Fforward to F from D, E, M, or W
30Which of these is a load-use hazard?
- Amrmovl (esi), %eax
addl %eax, %ebx - Brmmovl %eax, (esi)
addl %eax, %ebx
- Amrmovl (esi), %eax
31How would we handle a load-use hazard?
- AStall use one cycle, forward to D from M or W
- BStall use one cycle, forward to D from E or M
- CStall use one cycle, forward to E from D, M, or W
- DStall use one cycle, forward to E from M or W
32Jump prediction is not suitable for resolving conditional-jump hazards
- ARichtig
- BFalsch
33We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
- AE
- BD
- CM
- DW
34valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
- Anot taken
- Btaken
35When a mis-predicted jump is in M, what should we do?
- Ashootdown D and E to prevent them from doing damage
- Bshootdown F and D to prevent them from doing damage
- Cshootdown M and W to prevent them from doing damage
36The homework in this course is much too long
- ARichtig
- BFalsch
37We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
- ARichtig
- BFalsch
38We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
- ARichtig
- BFalsch
39In regards to static jump prediction, what could the compiler know?
- Aa jump's taken tendency
- Bfor loops, it can decide to use a continue condition or exit condition
- Cfor if statements it might be able to spot error tests
- Dwhat it sees in the program text
40The compiler cares about the ISA's jump predictions
- ARichtig
- BFalsch
41How do we optimize handling the return hazard?
- AKeep a stack of return addresses for future use
- BGuess the return address based on the value in predPC
- CGuess the return address based on the value in PC
- DGuess the return address based on the valP in D
42Y86 has indirect jumps
- ARichtig
- BFalsch
43Indirect jumps are needed for polymorphic dispatch
- ARichtig
- BFalsch
44CPI =
- AtotalCycles / instructionRetiredCycles
- BinstructionRetiredCycles / totalCycles
45What are the tendencies of deeper pipelines?
- Areduce clock period
- Bincrease CPI
- Cmakes stalling harder to avoid
46Which of these are attributes of super-scalar?
- Amultiple pipelines that run in parallel
- Bissue multiple instructions on each cycle
- Cinstructions execute in parallel and can even bypass each other
- Dif I shut my eyes tight enough, will the midterm disappear?
47What does hyper-threading consist of? (Only one of the following is correct)
- AOS loads multiple runnable threads into CPU, usually from the same process
- BCPU does fast switching between threads to hide memory latency
48What is multi-core?
- Amultiple CPUs per chip, each pipelined, super-scalar, etc
- BCPU's execute independent threads from possibly different processes
49How could Mike do this to us?
- ASadism
- BAlso sadism
- CAnd sadism
- DAll of the above
50In a pipelined processor, if you measure the time it takes for one instruction to completely execute, what have you measured?
- AThroughput
- BLatency
- CClock period.
- DNone of the above.
51In a pipelined processor, if you measure the total propagational delay (including stage-memory overhead) of the stage with the longest delay (i.e., the maximum stage delay), what have you measured?
- AThroughput
- BLatency
- CClock period
- DNone of the above
52In a pipelined processor, if you measure the total propagational delay (including stage-memory overhead) of every stage, what have you measured?
- AClock rate
- BThroughput
- CLatency
- DClock period
- ENone of the above
53In a pipelined processor, if you measure the average propagational delay (including stage-memory overhead) of every the pipeline's stages, what have you measured?
- AThroughput
- BLatency
- CClock period
- DNone of the above
54In a pipelined processor, if you measure the total propagational delay (including stage-memory overhead) of stage with the shortest delay (i.e., the minimum stage delay), what have you measured?
- AThroughput
- BLatency
- CClock period
- DNone of the above
55In a pipelined processor, the rate at which instructions are retired from the pipeline (i.e., finish executing), what have you measured?
- AThroughput
- BLatency
- CClock period
- DNone of the above
56In a pipeline that sometimes stalls, throughput is determined by clock rate.
- ARichtig
- BFalsch
57In the classic 5-stage pipeline with stages labeled (F, D, E, M and W, in that order). In a clock cycle where stage E must stall to avoid a hazard, which of the following statements is true.
- ANo other stage must stall, but stage M must bubble.
- BStages F and D must also stall, and stage M must bubble.
- COnly stages D (as well as E) must stall and stage M must bubble.
- DNo other stage must stall and stage M must bubble.
- EStages D and F must stall, but stage M need not bubble.
- FOnly stage D (as well as E) must stall and stage M need not bubble.
- GNo other stage need stall and M need not bubble.
- HSome stage or stages other than F and D must stall AND some stage or stages other than M must bubble.
- ISome stage or stages other than F and D must stall OR stage or stages other than M must bubble.
- JNone of the above.
58Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes
addl %ebx, %ecx # R[ecx] <= R[ebx] + R[ecx]; setting condition codes- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
59Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %ebx, %ecx # R[ecx] <= R[ebx] + R[ecx]; setting condiition codes
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
60Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
movl %eax, (%ebx) # M[R[ebx]] <= R[eax]; not setting condition codes
movl (%ebx), %ecx # R[ecx] <= M[R[ebx]]; not setting condition codes- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
61Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes
jne foo # jump to foo if and only if condition codes indicate last ALU result was not equal to zero- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions noris there a pipeline hazard.
62Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
rrmovl %eax, %ebx # R[ebx] <= R[eax]; not setting condition codes
jne foo # jump to foo if and only if the condition codes indicate that the result of the last ALU operation was not equal to zero- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
63Which of the following statements is true about the following two instructions when executed in sequence (i.e., one right after the other) in the 5-stage, Y86 pipeline we have discussed in class.
addl %eax, %ebx # R[ebx] <= R[eax] + R[ebx]; setting condition codes
jmp foo # jump to foo- AThere is a dependency between the two instructions and there is a pipeline hazard.
- BThere is a dependency between the two instructions but there is no pipeline hazard.
- CThere is no dependency between the two instructions but there is a pipeline hazard.
- DThere is neither a dependency between the two instructions nor is there a pipeline hazard.
64Which of the following statements best describes how the 5-stage Y86 pipeline handles anti and output dependencies.
- AThey are always handled with data forwarding and no stalls are required.
- BThey are handled with data forwarding, but stalls are sometimes required.
- CThey can not be handled with data forwarding and thus stalls are required.
- DThey are not hazards and thus the pipeline logic ignores them.
- EThey can be handled by dynamically renaming registers and thus neither data forwarding nor stalls are required.
65Which of the following statements best describes how the 5-stage Y86 pipeline handles causal dependencies on register access.
- AThey are always handled with data forwarding and no stalls are required.
- BThey are handled with data forwarding, but stalls are sometimes required.
- CThey can not be handled with data forwarding and thus stalls are required.
- DThey are not hazards and thus the pipeline logic ignores them.
66Which of the following statements best describes in general terms how a real processor (not Y86) would handle pipeline hazards due to anti and output dependencies.
- AThey are always handled with data forwarding and no stalls are required.
- BThey are handled with data forwarding, but stalls are sometimes required.
- CThey can not be handled with data forwarding and thus stalls are required.
- DThey are not hazards and thus the pipeline logic ignores them.
- EThey can be handled by dynamically renaming registers and thus neither data forwarding nor stalls are required.
67How many distinct data-forwarding paths are requied in the Y86 PIPE implementation. Note that a unique path is required for each pair of stage registers involed in forwarding (e.g., one path for d.srcA-M.dstE; another path for d.srcB-m.dstE, and so on)?
[blank_start]10[blank_end]- A10
68Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
addl %ebx, %eax # R[eax] <= R[ebx] + R[eax]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from E to D with no stall
- BForward from E to D with one stall.
- CForward from M to D with no stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
69Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
mrmovl (%ebx), %eax # R[eax] <= M[R[ebx]]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from E to D with no stall
- BForward from E to D with one stall.
- CForward from M to D with no stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
70Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
addl %ebx, %eax # R[eax] <= R[ebx] + R[eax]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from E to D with no stall
- BForward from E to D with one stall.
- CForward from M to D with no stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
71Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
mrmovl (%ebx), %eax # R[eax] <= M[R[ebx]]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from E to D with no stall
- BForward from E to D with one stall.
- CForward from M to D with no stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
72Which statement best describes how Y86 PIPE handles access to %eax in this sequence of instructions?
mrmovl (%ebx), %eax # R[eax] <= M[R[ebx]]
addl %esi, %edi # [Redi] <= R[esi] + R[edi]
addl %esp, %ebp # R[ebp] <= R[esp] + R[ebp]
rmmovl %eax, (%ecx) # M[R[ecx]] <= R[eax]- AForward from E to D with no stall
- BForward from E to D with one stall.
- CForward from M to D with no stall.
- DForward from M to D with one stall.
- EForwarding between two other stages (or in a different order) with no stall.
- FForwarding between two other stages (or in a different order) with one stall.
- GForwarding is not possible.
- HNone of the above.
73Which of the following statements best describes how Y86 pipe handles conditional jumps.
- AIt determines whether the jump is taken when the jump is in D.
- BIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in M.
- CIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in M.
- DIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in E.
- EIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in E and (2) selects a new PC value for F when the jump is in E.
- FIt predicts that the jump is taken when it is in D and if it later determines that the jump was not taken, it (1) bubbles D and E when the jump is in M and (2) selects a new PC value for F when the jump is in M.
- GIt predicts that the jump is not taken when it is in D and if it later determines that the jump was taken, it (1) bubbles D and E when the jump is in M and (2) selects a new PC value for F when the jump is in M.
- HNone of the above.
74The implementation of jump (branch) prediction involves two circuits named "Select PC" and "Predict PC". "Select PC" reads F.prPC and sets f.pc and "Predict PC" sets f.prPC. Which statement bests describes the relationship between these two circuits.
- A"Predict PC" must complete its computation before "Select PC" can begin, because the output of "Predict PC" is the input to "Select PC".
- B"Predict PC" and "Select PC" can procede in parallel, but the clock period must be long enough so that "Select PC"'s output reflects the prPC value computed by "Predict PC" in that cycle.
- C"Predict PC" and "Select PC" can procede in parallel beacuse the value computed by "Predict PC" in cycle i is not used in cycle i by "Select PC.
- D"Predict PC" and "Select PC" can proceded in parallel because the value computed by "Predict PC" can be sent to "Select PC" via data fowarding.
75When a jump (branch) mis-prediction is detected, the fetch stage must select a new instruction to enter the pipeline to replace the mispredicted instructions that are being shotdown by the pipeline-control circuit. Which of the following best describes how the fetch stage does this.
- AThe values of bch/cnd and valP are forward to F from the end of E so that F can change to the PC to valP.
- BThe values of bch/cnd and valP are foward to F from the beginning of M so that F can change the pc to valP
- CThe values of bch/cnd and valC are forward to F from the end of E so that F can change to the PC to valPC.
- DThe values of bch/cnd and valC are foward to F from the beginning of M so that F can change the pc to valC
76Which statement best describes the pipeline impact of a mispredicted jump.
- AIt causes one stall.
- BIt causes one bubble.
- CIt causes two stalls.
- DIt causes two bubbles.
- EIt causes three stalls.
- FIt causes three bubbles.
77Comparing static and dynamic jump prediction, which statement best describes the advantage (if any) the compiler has over the pipeline.
- AThe compiler can spend more time analyzing a program and so can more easily determine which portions of code are more likely to be executed by examining the dynamic nature of the program (e.g., in if statements).
- BThe compiler sees more of the program at once compared to the pipeline and so can more easily determine whether jumps will normally be taken by examining the only static structure of the program; dynamic information is not useful for jump prediction.
- CThe pipeline is better at examining the dynamic nature of the program and this information is typically more useful than information the compiler can gather and so both can be involved, but priority should be given to the pipeline.
- DThe pipeline is better at examining the dynamic nature of the program, but this information is not aways as useful as information the compiler can gather and so both should be involved, but priority should be given to the compiler.
78Consider what (if anything) should be specified in the instruction set architecure (ISA) about how a processor implementation should handle jump prediction.
- AThe ISA should not specify anything; it should instead give hardware implementations the flexibility to implement jump prediction in best way permitted by current technology.
- BThe ISA should specify that all jumps must be predicted taken.
- CThe ISA should specify that jumps are normally taken but that dynamic information can be used to predict a jump is not taken if and only if recently history of that jump indicates that it was mostly not taken.
- DThe ISA should specify that a jump is taken but that dynamic information can be used to predict that a jump is not taken and that this prediction should be kept simple; for example, it would be permissible to predict a jump is not taken if it was not taken the last time it executed.
79Which of the following statemetns best describes how pipelines should generally handle the return-instruction (i.e., ret) control hazard.
- AThere is no choice but to stall the instruction immediately following ret, because the address of that instruction can not be know until ret finishes M.
- BIt is possible to use a strategy similar to jump prediction to avoid stalling sometimes, but that prediction may sometimes be wrong in which case bubbles will be required.
- CIt is possible to avoid stalling by caching information from certain other instructions when they pass through the pipeline, but this prediction may sometimes be wrong in which case bubbles will be required.
- DIt is possible to avoid stalling by caching information from certain other instructions when they pass through the pipeline. There may be times when this strategy can not be used and thus stalling is required; but when it is used, the prediction is always correct and thus subsequent "bubbling" is not required.
80Which of the following statements best describes the comparsion between the pipeline impact of the return instruction and the double-indirect jump instruction (i.e, where the jump target is stored in memory, not in the instruction).
- AIt is harder to handle the ret instruction without stalling.
- BThe instructions are too different for there to be any meaningful comparison.
- CIt is harder to handle the double-indirect jump instruction without stalling.
- DStalling can be avoided for both instructions by following the same strategy.
81What type of parallism (if any) are pipelined architectures designed to exploit?
- Ainstruction-level parallism
- Bthread-level parallism
- Cboth
- Dneither
82What type of parallism (if any) are super-scalar architectures designed to exploit?
- Ainstruction-level parallism
- Bthread-level parallism
- Cboth
- Dneither
83What type of parallism (if any) are hyper-threaded architectures designed to exploit?
- Ainstruction-level parallism
- Bthread-level parallism
- Cboth
- Dneither
84What type of parallism (if any) are multi-core architectures designed to exploit?
- Ainstruction-level parallism
- Bthread-level parallism
- Cboth
- Dneither
85Match the statement to the architectural feature:
[blank_start]processor pipelining[blank_end] = Instructions complete in order, but are executed partially in parallel, as permitted by available instruction-level parallelism.
[blank_start]super scalar processors[blank_end] = Instructions are executed in parallel and possibly out of order, as permitted by available instruction-level parallelism.
[blank_start]Hyper threading[blank_end] = One thread executes at a time, but memory stalls are hidden by switching from one thread to another (in a single cycle), as permitted by available thread-level parallelism.
[blank_start]Multi-core[blank_end] = Multiple threads can execute in parallel (i.e., at the same time), as permitted by available thread-level parallelism- Aprocessor pipelining
- Bsuper scalar processors
- CHyper threading
- DMulti-core
86Which of the following statements best describes SRAM.
- AEach bit requires fewer transistors than DRAM and thus it is less expensive but slower.
- BEach bit requires fewer transistors than DRAM and thus it is less expensive and faster.
- CEach bit requires more transistors than DRAM and thus it is more expensive but faster.
- DEach bit requires more transistors than DRAM and thus it is more expensive and slower.
87All other things being equal, bigger memories are always slower.
- ARichtig
- BFalsch
88All other things being equal, bigger memories are only slower if they are located off-chip (i.e., not on the same chip as the processor).
- ARichtig
- BFalsch
89The access-latency difference between the register file and main memory is roughly the same magnitude as the difference between main memory and disks (i.e.,hard drives).
- ARichtig
- BFalsch
90Which of the following statements best describes the relationship between the regisger file and the L1 cache?
- AThe register file is much faster (i.e. has lower access latency) and instructions that access it are the same size as instructions that access the L1 cache.
- BThe register file is much faster and instructions that access it are smaller than instructions that access the L1 cache.
- CThey have roughly the same access latency and instructions that access the register file are the same size as instructions that access the L1 cache.
- DThey have roughly the same access latency but instructions that access the register file are smaller than instructions that access the L1 cache.
Informationen
- Beschreibung
- Unit 2 of UBC's CS313 course. Get some alcohol.
- Autor
- Zim Brightwood
- Sprache
- English
- Aufrufe
- 6
- Schlagwörter
- Bewertung
- Noch keine Bewertungen Bewerte dieses Quiz