130. How many bytes equals Petabyte (PB)?
· Quadrillion
· Million
· Trillion
· Billion
· 1000
129. Which one of the following is a memory whose duty is to store most frequently used data?
· Main memory
· Cache
· ROM
· Auxiliary memory
· PROM
128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
· Binary Adder
· Full Adder
· Half Adder
· Adder
· OR gate
127. The key technology used in IV generation computers is ___.
· MSI
· SSI
· LSI & VLSI
· Transistors
· Vacuum Tubes
126. The computer architecture having stored program is ___.
· Harvard
· Von Neumann
· Pascal
· Ada
· Cobol
125. Stack is a ___list.
· FIFO
· LIFO
· FILO
· OFLI
124. CACHE memory is implemented using ___.
· Dynamic RAM
· Static RAM
· EA RAM
· ED RAM
· EP RAM
123. What does D stand for in a D flip-flop?
· Direct
· Don’t care
· Data
· Device
· Disk
104. What is a Capacity?
· cache is too small to hold all data needed by program, occur even under perfect replacement policy
· first-reference to a block, occur even with infinite cache
· misses that occur because of collisions due to less than full associativity
103. What is a Compulsory?
39. 74. How many elements of the Instruction Set Architecture (ISA)
8
7
6
38. 73. What is the MISD one of the categories of computers?
Multiple Instruction Streams, Multiple Data Streams
Multiple Instructions Streams, Single Data Stream
Multiple Instruction Streams, Set Data Stream
36. 72. What is the Instruction Level Parallelism
Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
35. 71. What is the Request Level Parallelism
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
34. 70. What is the Thread Level Parallelism
33. 69. What is the Vector Architectures and Graphic Processor Units (GPUs)
32. 68. The Application of Brokerage operations how many cost of downtime per hour?
8.870.000$
7.550.000$
6.450.000$
31. 67. What is the PMD in computer classes?
Percentage map device
Personal mobile device
Peak maze development
Powerful markup distance
30. 66. Which distance of price has Clusters/warehouse-scale computers?
100 – 100.000$
100.000 – 200.000.000$
5.000 – 10.000.000$
29. 65. How many classes of computers classified?
3
5
28. 64. What is the RLP?
Request Level Parallelism
Research Level Parallelism
Random Level Parallelism
27. 63. How much in percentage single-processor performance improvement has dropped to less than?
22%
33%
11%
26. 62. When single-processor performance improvement has dropped?
2003
2002
2004
25. 61. What is a RISC computers?
Rational Interruptible Security Computer
Research Interconnect Several Computer
Reduced Instruction Set Computer
24. 56. Choose the right formula of AMAT(в базе был неверный ответ можете попробовать подать апелляцию)
Average Memory Access time = Hit Time + Miss Rate * Miss penalty
Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
Average Memory Access time = Hit Time + Miss time * Miss penalty
Average Memory Access time = Hit Rate + Miss time * Miss penalty
23. What is the total number of writes that hit in the cache?
588
784
12.5%
0.25%
22. 30. Definition of Block address:
minimum unit that is presented or not present
location of block in memory
percentage of item not found in upper level
time to access upper level
memory closer to processor
20. 28. Definition of Block:
19. 27. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
SRAM
DRAM
RAM
18. 26. Performance of a machine is determined by:
Instruction count, Clock cycle time, Correlating predictors
Instruction count, Clock cycle time, Clock cycle per instruction
Clock cycle time, Correlating predictors, Aggressive instruction
Clock cycle time, Clock cycles per instruction, Correlating Predictors
17. 25. Pipe-lining is a unique feature of ___.
CISC
IANA
ISA
RISC
16. 24. The iconic feature of the RISC machine among the following are
Increased memory size
Reduced number of addressing modes
Having a branch delay slot
All of the above
15. 23. The Sun micro systems processors usually follow ___ architecture.
ULTRA SPARC
14. 22. Of the following, identify the memory usually written by the manufacturer.
ROM
Cache Memory
13. 21. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
Hit rate
Miss rate
Access rate
Success rate
12. 20. How many instructions can be implemented in MIPS?
2 clock cycles
3 clock cycles
4 clock cycles
5 clock cycles
19. The secondary effect that results from instruction scheduling in large code segments is called ___?
Aggressive instruction
Correlating predictors
Register predictors
Register pressure
10. 18. The CISC stands for?
Computer Instruction Set Compliment
Complete Instruction Set Compliment
Computer Indexed Set Components
Complex Instruction Set Computer
9. Assembly line operation is also called as?
Pipelining process
Superscalar operation
None of the mentioned
Von Neumann cycle
8. 16. Can you solve the Dining Philosophers’ Problem using monitors?
Yes
No
Yes, but only if there are less than five philosophers
No, unless there are more than five philosophers
7. 15. The central themes of operating system design are all concerned with the management of processes and threads?
Multiprogramming, multiprocessing, distributed processing
Multitasking, multiprogramming, multithreading
Multiprocessing, uniprocessing, multitasking
Multithreading, distributed processing, uniprocessing
6. 14. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Availability, confidentiality, data integrity, authenticity
Safety, accountability, reliability, density
Usability, integrity, confidentiality, reliability
Flexibility, availability, accountability, authenticity
5. 13. Which of the following principles has Deadlock?
Execution, Association, Starvation
Prevention, Avoidance, Detection
Starvation, Detection, Exclusion
Exclusion, Avoidance, Starvation
4. 12. How many principles has Deadlock?
2
3. 11. Three techniques are possible for I/O operations:
Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
Machine I/O, Architecture I/O, Hardware I/O
Object-oriented I/O, Design I/O, Usable I/O
Control I/O, Status I/O, Transfer I/O
2. 10. Cache Design has these properties?
Size, search function, write function, read policy, vector algorithm
Size, mapping algorithm, vector function, write policy, replacement function
Size, blocking algorithm, search function, replacement vector, read policy
Size, block size, mapping function, replacement algorithm, write policy
1. In Memory Hierarchy, at the Inboard storage which of the following are included:
Magnetic disk
Magnetic tape
Optical disk
Main memory
180. In Memory Hierarchy, at the Off-line storage which of the following are included:
• Cache
• Magnetic disk
• Magnetic tape
• Main memory
179. In Memory Hierarchy, at the Outboard storage which of the following are included:
178. How many parts of Memory Hierarchy?
• 5
• 4
• 2
• 3
177. Which one is concerning to fallacy?
o Predicting cache performance of one program from another
o Simulating enough instructions to get accurate performance measures of the memory hierarchy
o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
o Over emphasizing memory bandwidth in DRAMs
176. Which one is NOT concerning to pitfall?
175. ChoosetheEleventhOptimization
o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
o Merging Write Buffer to Reduce Miss Penalty
o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
o None of them
174. ChoosetheEightOptimization
o Critical word first
o Nonblocking Caches to Increase Cache Bandwidth
o Trace Caches to Reduce Hit Time
173. Choose the strategy of Seventh Optimization.
o Critical restart
o Sequential inter leaving
172. Choose the benefit of Cache Optimization.
o Larger block size to reduce miss rate
o Bigger caches to increase miss rat
o Single level caches to reduce miss penalty
171. What is conflict in Cs model?
o If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
170. What is capacityin Cs model?
o The number of accesses that miss divided by the number of accesses.
169. What is the compulsory in Cs model?
168. How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
o the number of prediction entries selected by the branch = 1K.
o the number of prediction entries selected by the branch = 2K.
o the number of prediction entries selected by the branch = 8K.
o the number of prediction entries selected by the branch = 4K.
167. Branch predictors that use the behavior of other branches to make a prediction are called
o correlating predictors or two-level predictors
o branch-prediction buffer
o branch table
o three level loop
166. The simplest dynamic branch-prediction scheme is a
o branch buffer
o All answers correct
o registrationo registration
165. Effect that results from instruction scheduling in large code segments is called…?
o register pressure
o loop unrolling
o loop-level
o registration
164. A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
o RAR
o loop rolling
163. What is given is not a hazard?
o WAR
o WAW
o LOL
162. What is RAW (read after write)?
o when j tries to read a source before i writes it, so j incorrectly gets the old value
o when j tries to write a source before i writes it
o when i tries to read a source before j writes it, so j correctly gets the old value
o when a tries to write a source before b read it, so a incorrectly gets the old value
161. When occurs an output dependence?
o When i and instruction j write the same register or memory location
o when i and instruction j write the same adress or memory location
o when i and instruction j write the same name
o All answers is correct
160. What is Name dependence?
o name dependence occurs when two instructions use the same register or memory location
o name dependence occurs when five or more instructions use the same register or memory location
o name dependence occurs when instructions use the same name
159. In parallelism have three different types of dependences, tagging him:
o data dependences , name dependences , and surname dependences
o datagram dependences , name dependences , and animal dependences
o no correct answers
o data dependences , name dependences , and control dependences
158. The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
o loop-level parallelism
o exploit-level parallelism
o high-level minimalism
o low-level minimalism
157. The simplest and most common way to increase the ILP is …?
o to exploit parallelism among iterations of a loop
o to exploit minimalism among iterations of a loop
o to destroy iterations of a loop
o to decrease the minimalism of risk
156. What is the Pipeline CP = ?
o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
o deal pipeline CPU + Data hazard stalls + Control stalls
o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
o Structural stalls + Data hazard stalls + Control stalls
155. The ideal pipeline CPI is a measure of …
o the maximum performance attainable by the implementation
o the maximum performance attainable by the instruction
o the minimum performance attainable by the implementation
o the minimum performance attainable by the instruction
154. How to decrypt RISC?
o Reduced Instruction Set Computer
o Recall Instruction Sell Communication
o Rename Instruction Sequence Corporation
o Red Instruction Small Computer
153. What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
o Address aliasing prediction
o Branch prediction
o Integrated branch prediction
o Dynamic branch prediction
152. Which is not the function of integrated instruction fetch unit:
o Instruction memory commit
o Instruction memory access and buffering
o Instruction prefetch
151. Buffering the actual target instructions allows us to perform an optimization which called:
o branch folding
o Target instructions
o Target address
150. A branch-prediction cache that stores the predicted address for the next instruction after a branch
o branch-target buffer
o data buffer
o frame buffer
o optical buffer
149. Examples of VLIW/LIW:
o TI C6x
o MIPS and ARM
o Itanium
o Pentium 4, MIPS R12K, IBM, Power5
148. Examples of superscalar(dynamic) :
o None at the present
147. Examples of superscalar(static):
• MIPS and ARM
146. Examples of EPIC:
145. Which Multiple-issue processors has not the hardware hazard detection:
o EPIC
o Superscalar(dynamic)
o Superscalar(static)
o Superscalar(speculative)
144. Which one is not the major flavor of Multiple-issue processors:
o statistically superscalar processors
o dynamically scheduled superscalar processors
o statically scheduled superscalar processors
o VLIW (very long instruction word) processors
143. Choose the steps of instruction execution:
o issue, execute, write result, commit
o execution, commit, rollback
o issue, execute, override, exit
o begin, write, interrupt, commit
142. Choose correct fields of entry in the ROB:
o the instruction type, the destination field, the value field, and the ready field
o the source type, the destination field, the value field, and the ready field
o the program type, the ready field, the parameter field, the destination field
o the instruction type, the destination field, and the ready field
141. How many fields contains the entry in the ROB:
4
140. For what the reorder buffer is used :
o To pass parameters through instructions that may be speculated
o To pass results among instructions that may be speculated.
o To get additional registers in the same way as the reservation stations
o To control registers
139. How this process called: “Operations execute as soon as their operands are available”
o data flow execution
o data control execution
o instruction execution
o instruction field execution
138. Which of these is NOT characteristics of recent highperformance microprocessors?
o Color
o Functional unit capability
o Clock rate
o Power
• Popular data structure for organizing a large collection of data items so that one can quickly
o Popular data structure for organizing a large collection of data items so that one can quickly answer questions
o Popular tables for organizing a large collection of data structure
o Popular data structure for updating large collections, so that one can hardly answer questions
o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
o Achievable ILP with software resource constraints
o Limited ILP due to software dependences
o Achievable ILP with hardware resource constraints
o Variability of ILP due to software and hardware interaction
135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
o Dynamic power
o Processing rate
o Static power
o Processor state
134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
133. If we want to sustain four instructions per clock
o We must fetch more, issue more, and initiate execution on more than four instructions
o We must fetch less, issue more, and initiate execution on more than two instructions
o We must fetch more, issue more, and initiate execution on less than five instructions
o We must fetch more, issue less, and initiate execution on more than three instructions
132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
o The number of transistors switching will be proportional to the sustained rate
o The performance is proportional to the peak issue rate
131. Which of the written below is NOT increase power consumption?
o Increasing multithreading
o Increasing performance
o Increasing multiple cores
o Increasing multithreading(повторяется хз что тут )
130. Which of the following descriptions corresponds to dynamic power?
o Proportional to the product of the number of switching transistors and the switching rate
o Grows proportionally to the transistor count (whether or not the transistors are switching)
o Certainly a design concern
o None of the above
129. Which of the following descriptions corresponds to static power?
o Proportional to the product of the number of switching transistors and the switching rate Probability
o All of the above
128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
o Speedup
o Efficiency
o Probability
o Ration
127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
• 90% 10%
o 70% 30%
o 50% 50%
o 89% 11%
126. What MTTF means:
o mean time to failure
o mean time to feauture
o mean this to failure
o my transfers to failure
125. Desktop benchmarks divide into __ broad classes:
o two
o three
o four
o five
124. Systems alternate between two states of service with respect to an SLA:
o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
123. The most companies spend only ____________ of their income on R&D, which includes all engineering.
o 30% to 48%
o 4% to 12%
o 15% to 30%
o 1% to 17%
122. Volume is a ________ key factor in determining cost.
o second
o first
o fifth
o third
121. Manufacturing costs that decrease over time are ____
o the learning curve
o the cycled line
o the regular option
o the final loop
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
o dynamic power
o physical energy
o constant supply
o simple battery
119. Integrated circuit processes are charecterized by the
o feature size
o permanent size n
o compex size
o fixed size
118. Products that are sold by multiple vendors in large volumes and are essentialy identical
o boxes
o files
o folders
o commodities
117. Learning curve itself is best measured by change in...
o bytes
o bits
o seconds
o yeld
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer...
o bandwidth
o throughput
o latency
o performance
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
1. Network performance depends of what?
o performance of swithes and transmission system
o performance of switches
o has no dependensies
o performance of transmission system
113. What is a “Kernel” in Cache Memory?
o Execution in the OS that is neither idle nor in synchronization access
o Execution or waiting for synchronization variables
o Execution in user code
112. What is a “Synchronization” in Cache Memory?
111. What is a “Kernel” in Cache Memory?
110. What is a “Synchronization” in Cache Memory?
