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Computer Architecture Test 3 Prep

Robert Parson 23 preguntas

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Preguntas del test (23)

  1. 1A ______ may sometimes be ignored by the CPU.
    1. Apage fault
    2. Bnon-maskable interrupt
    3. Ctrap
    4. Dmaskable interrupt
    5. Enone of the above
    6. FAll of the above
  2. 2In a 16-node system, which of these networks would have the largest communication diameter?
    1. An-cube
    2. Btwo-dimensional nearest neighbor mesh
    3. Cring
    4. Dtorus
  3. 3Which of the following is a rearrangeable interconnection network?
    1. AIlliac network
    2. BOmega network
    3. Ccrossbar switch
    4. DBenes Network
    5. EAll except crossbar switch
    6. Fnone of the above
  4. 4Which of the following architectures uses memory-mapped I/O?
    1. AIntel x86
    2. BMotorola 6811C12
    3. CMotorola 680x0
    4. DSun SPARC
    5. ENone of the above
    6. FAll except Intel x86
  5. 5In a 64-node system, which of the following would have the smallest node connection degree?
    1. Aring
    2. Btwo-dimensional nearest-neighbor mesh
    3. CIlliac Network
    4. Dn-cube
  6. 6In "Big 0" notation, the cost of an n-to-n Omega network can be expressed as:
    1. AO(n)
    2. BO(n log n)
    3. CO( n²)
    4. DO(log n)
    5. Enone of the above
  7. 7Which type of architecture is modeled on the structure of a biological brain?
    1. Afuzzy logic processor
    2. Bdataflow computer
    3. Cquantum computer
    4. Dartificial neural network
    5. Enone of these
    6. Fall of these
  8. 8Which of the following architectures provides support for separate I/O?
    1. AMotorola 680x0
    2. BMotorola 68HC12
    3. CSun SPARC
    4. DIntel x86
    5. Enone of these
    6. Fall of these
  9. 9Which of the following is not a method for ensuring cache coherence in a multiprocessor system where each processor has its own cache?
    1. Awrite-update snoopy cache
    2. Bwrite-through cache
    3. Cwrite-invalidate snoopy cache
    4. Dfull-map directory protocol
    5. Eany of the above methods is sufficient to ensure coherence
  10. 10A special read-modify-write bus cycle is needed to support _______.
    1. ANon-Maskable Interrupts
    2. BDirect Memory Access (DMA)
    3. CIndivisible Access to Semaphores
    4. DAll of the above
    5. ENone of the above

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Quiz on Test 3 Prep, created by Robert Parson on 18/11/2017.
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