Test
CSA Last p2
Crea una cuenta gratis para terminar este test
Guarda tu progreso y consulta tu resultado final.
¿Ya tienes cuenta? Inicia sesión
Preguntas del test (70)
1Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
- AInteger Datapath
- BCLK
- CFree List
- DAddress Queue
2What is “VLIW”?
- AVery Long Instruction Word
- BVery Less Interpreter Word
- CVery Light Internal Word
- DVery Low Invalid Word
3At VLIW by “performance and loop iteration” which time is longer?
- ALoop Unrolled
- BSoftware Pipelined
4At VLIW by “performance and loop iteration” which time is shorter?
- ASoftware Pipelined
- BLoop Unrolled
5At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- ASpeculative operations that don’t cause exceptions
- BHardware to check pointer hazards
6At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- AHardware to check pointer hazards
- BSpeculative operations that don’t cause exceptions
7What is an ALAT? :
- AAdvanced Load Address Table
- BAllocated Link Address Table
- CAllowing List Address Table
- DAddition Long Accessibility Table
8At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- AAllow one instruction to branch multiple directions
- BSpeculative operations that don’t cause exceptions
9What is a Compulsory?
- Afirst-reference to a block, occur even with infinite cache
- Bcache is too small to hold all data needed by program, occur even under perfect replacement policy
- Cmisses that occur because of collisions due to less than full associativity
10What is a Capacity?
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy
- Bfirst-reference to a block, occur even with infinite cache
- Cmisses that occur because of collisions due to less than full associativity
11Convert this number systems: DEC (9578) to HEX?
- A256A
- B43B1
- C7DE1
- DA31F
12Convert this number systems: DEC (9845) to HEX?
- A2675
- B2798
- C2945
- D2811
13Define a boolean algebra
- Aprocess that applies binary logic to yield binary results
- Bto determine whether an IP address exists on the local network or whether it must be routed outside the local network.
- CIt sends out ICMP (Internet Control Message Protocol) messages to verify both the logical addresses & the Physical connection.
- Dto determine whether an IP address exists on the global network or whether it must be routed outside the global network.
14Where Virtual Machine was developed?
- ALancaster University
- BManchester University
- CMIT
- DCambridge
15What is the first commercial computer with virtual machine
- AB5000
- BB5550
- CB5500
- DC5000
16When was the first commercial computer with virtual machine released?
- A1961
- B1962
- C1963
- D1964
17Which of the following is false about VM and performance?
- ABetter performance: we can use more memory than we have
- BNothing; mapping to memory or disk is just as easy
- CWorse performance: reading from disk is slower than RAM
- DGood performance: reading from disk is slower than RAM
18Which of the following is false about usability of Virtual Memory?
- ANot enough memory
- BHoles in the address space
- CKeeping program secure
- DKeeping program insecure
19Define virtual address space
- Aprocess refers to the logical (or virtual) view of how a process is stored in memory
- Bused to translate the virtual addresses seen by the application into physical addresses
- Ca segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
- Dnone of the mentioned
20Define a page tables
- Aprocess refers to the logical (or virtual) view of how a process is stored in memory
- Bused to translate the virtual addresses seen by the application into physical addresses
- Ca segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
- Dnone of the mentioned
21Of the following, identify the memory usually written by the manufacturer.
- ARAM
- BDRAM
- CSRAM
- DROM
- ECache Memory
22Multi-processor system that computer system have are also called
- Aparallel; systems
- Btightly coupled system
- Cloosely coupled system
- Dboth a and b
23Which of the following statement is false?
- ACombinational circuits has memory
- BSequential circuits has memory
- CSequential circuits is a function of time
- DCombinational circuits does not require feedback paths
- ESequential circuits require feedback paths.
24The computer architecture having stored program is _____.
- AHarvard
- BVon-Neumann
- CPascal
- DAda
- ECobol
25The key technology used in IV generation computers is _______.
- AMSI
- BSSI
- CLSI &VLSI
- DTransistors
- EVacuum Tubes
26The digital circuit that generates the arithmetic sum of two binary numbers of any length is ________ .
- ABinary-Adder
- BFull-Adder
- CHalf-Adder
- DAdder
- EOR-gate
27Serial to parallel data conversion is done using
- AAccumulator
- BShift Register
- CCounter
- DCPU
- EControl Unit
28CACHE memory is implemented using ________.
- ADynamic RAM
- BStatic RAM
- CEA RAM
- DED RAM
- EEP RAM
29Stack is a _________list.
- AFIFO
- BLIFO
- CFILO
- DOFLI
- ELFIO.
30Which one of the following is a memory whose duty is to store most frequently used data?
- AMain memory
- BCache memory
- CROM
- DAuxiliary memory
- EPROM.
31How many bytes equals Petabyte (PB)?
- AQuadrillion
- BMillion
- CTrillion
- DBillion
- E1000
32Examples of superscalar(static):
- AMIPS and ARM
- BPentium 4, MIPS R12K, IBM, Power5
- CItanium
- DTI C6x
33Examples of superscalar(dynamic) :
- ANone at the present
- BPentium 4, MIPS R12K, IBM, Power5
- CMIPS and ARM
- DTI C6x
34How many main levels of Cache Memory?
- A3
- B2
- C6
- D8
35What is a “Synchronization” in OS Execution?
- AExecution in the OS that is neither idle nor in synchronization access
- BExecution in user code
- CExecution or waiting for synchronization variables
36What is a “Kernel” in OS Execution?
- AExecution or waiting for synchronization variables
- BExecution in the OS that is neither idle nor in synchronization access
- CExecution in user code
37Which one of the following is correct?
- ASequential circuit is an interconnection of only logic gates
- BSequential circuit is an interconnection of only flip flops
- CCombinational circuit is an interconnection of logic gates
- DCombinational circuit is an interconnection of flip flops
- EPart of a combinational circuit is a sequential circuit.
38Identify the expansion for RISC.
- AReduced Instruction Sign Computers
- BReduced Instruction Set Computers
- CReduced Instruction Set Carry
- DReduced Invalid Set Computers
- EReset Instruction Set Computers.
39Buffering the actual target instructions allows us to perform an optimization which called:
- Abranch folding
- BBranch prediction
- CTarget instructions
- DTarget address
40Which is not the function of integrated instruction fetch unit:
- AInstruction memory commit
- BIntegrated branch prediction
- CInstruction prefetch
- DInstruction memory access and buffering
41What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
- AAddress aliasing prediction
- BBranch prediction
- CIntegrated branch prediction
- DDynamic branch prediction
42RISC stands for
- AReduced Instruction Set Computer
- BRecall Instruction Sell Communication
- CRename Instruction Sequence Corporation
- DRed Instruction Small Computer
43The ideal pipeline CPI is a measure of …
- Athe maximum performance attainable by the implementation
- Bthe maximum performance attainable by the instruction
- Cthe minimum performance attainable by the implementation
- Dthe minimum performance attainable by the instruction
44What is the Pipeline CPI ?
- AIdeal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
- BIdeal pipeline CPU + Data hazard stalls + Control stalls
- CIdeal pipeline CPU + Ideal pipeline CPI + Data hazard stalls + Control stalls
- DStructural stalls + Data hazard stalls + Control stalls
45The simplest and most common way to increase the ILP is …?
- Ato exploit parallelism among iterations of a loop
- Bto exploit minimalism among iterations of a loop
- Cto destroy iterations of a loop
- Dto decrease the minimalism of risk
46The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
- Aloop-level parallelism
- Bexploit-level parallelism
- Chigh-level minimalism
- Dlow-level minimalism
47In parallelism have three different types of dependences, tagging him:
- Adata dependences, name dependences and control dependences
- Bdata dependences, name dependences, and surname dependences
- Cdatagram dependences ,name dependences, and animal dependences
- Dno correct answers
48What is Name dependence?
- Aname dependence occurs when two instructions use the same register or memory location
- Bname dependence occurs when five or more instructions use the same register or memory location
- Cname dependence occurs when instructions use the same name
- DAll answers is correct
49When occurs an output dependence?
- AWhen i and instruction j write the same register or memory location
- Bwhen i and instruction j write the same name
- Cwhen i and instruction j write the same address or memory location
- DAll answers is correct
50What is RAW (read after write)?
- Awhen j tries to read a source before i writes it, so j incorrectly gets the old value
- Bwhen i tries to read a source before j writes it, so j correctly gets the old value
- Cwhen j tries to write a source before i writes it
- Dwhen a tries to write a source before b read it, so a incorrectly gets the old value
51What is given is not a hazard?
- ARAR
- BWAR
- CWAW
- DRAW
52A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
- Aloop unrolling
- BRAR
- Cloop-level
- Dloop rolling
53Effect that results from instruction scheduling in large code segments is called…?
- Aregister pressure
- Bloop unrolling
- Cloop-level
- Dregistration
54The simplest dynamic branch-prediction scheme is a
- Abranch-prediction buffer
- Bbranch buffer
- CAll answers correct
- Dregistration
55Branch predictors that use the behavior of other branches to make a prediction are called
- Acorrelating predictors or two-level predictors
- Bbranch-prediction buffer
- Cbranch table
- Dthree level loop
56What is the compulsory in Three C’s model?
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- BIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- CThe number of accesses that miss divided by the number of accesses.
- DNone of them
57What is capacity in Three C’s model?
- AIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- CThe number of accesses that miss divided by the number of accesses.
- DNone of them
58What is conflict in Three C’s model?
- AIf the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- CIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- DNone of them
59Which of the following belongs to Cache Optimization?
- ALarger block size to reduce miss rate
- BBigger caches to increase miss rat
- CSingle level caches to reduce miss penalty
- DNone of them
60Choose the strategy of Sixth Cache Optimization
- ACritical word first
- BCritical restart
- CSequential inter leaving
- DMerging Write Buffer to Reduce Miss Penalty
61Choose the Seventh Cache Optimization
- AMerging Write Buffer to Reduce Miss Penalty
- BCritical word first
- CNonblocking Caches to Increase Cache Bandwidth
- DTrace Caches to Reduce Hit Time
62Choose the Tenth Cache Optimization
- ACompiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
- BMerging Write Buffer to Reduce Miss Penalty
- CHardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
- DNone of them
63What is the access time?
- ATime between when a read is requested and when the desired word arrives
- BThe minimum time between requests to memory.
- CDescribes the technology inside the memory chips and those innovative, internal organizations
- DNone of them
64What is the cycle time?
- AThe minimum time between requests to memory.
- BTime between when a read is requested and when the desired word arrives
- CThe maximum time between requests to memory.
- DNone of them
65What does DRAM stands for?
- ADynamic Random Access memory
- BDual Random Access memory
- CDataram Random Access memory
66What does DDR stands for?
- ADouble data rate
- BDual data rate
- CDouble data reaction
- DNone of them
67What acts as the traffic cop controlling the flow of data and coordinating interactions among components in the system?
- AMicroprocessor
- BMain memory
- CStorage device
- DChipset
68Instruction register stores_____________?
- AData of the current instruction
- BNext Instruction which is to be executed
- CAddress of the current instruction
- DInstruction which is currently executed
69A Set of Physical Addresses is called ________________?
- APages
- BAddress space
- CDisk space
- DMemory space
70The ______________________ operation sets to 1 the bits in one register where there are corresponding?
- ASelective Clear
- BMask
- CSelective Complement
- DSelective Set
Información
- Descripción
- Test sobre CSA Last p2, creado por Last Quickly el 30/03/2019.
- Autor
- Last Quickly
- Idioma
- English
- Visitas
- 203
- Valoración
- Aún sin valoraciones Valora este test