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Preguntas del test (30)
1What is the typical organization of a centralized shared memory?
- APrivate caches of the multiprocessors may replicate content of the remote main memory.
- BBy replicating shared data in private memory, each processor can operate on its data without worrying about interferences from other processors.
- CPrivate memory is connected directly to a chip via a memory bus and shared among all cores on the chip.
- DA memory shared by all processors is divided among the processors to be their private memories
2What is the cache coherence problem?
- ASince multiple caches exist to serve different processors, the content of the different caches may not be identical.
- BSince data of the main memory are cached by different processors, the processors could be seeing different values for the same memory location,
3Which of the following conditions are required for a memory system to be coherent?
- AIf a processor p1 first writes a value V to a location X and then try reads location X, with no other writes to X by other processors in between, the read is guaranteed to return V (the value written by P).
- BIf a processor p1 first writes a value V1 to a location X, and then another process P2 writes V2 to location X, all processors trying to read location X must be seeing V1 first before seeing V2
- CIf a processor p1 first writes a value V1 to a location X, and then another process P2 writes V2 to location X. The same ordering of V1 and V2 must be observed by all processors.
- DIf a processor p1 first writes a value V to a location X, and then another processor P2 tries to read location X, with no other writes to X in between, the read by P2 is guaranteed to return value V, if sufficient time has passed between the write by P1 and read by P2.
4Which of the following define cache coherence protocols in multiprocessors?
- AThe state of any shared data block must be tracked, by using status bits associated with the block.
- BIn directory-based protocols, the sharing status of a block is kept in one centralized location called the directory.
- CIn snoop-based protocals, the sharing status of a block is tracked by every cache that has the data, and all cache controllers monitor or snoop on a global bus to determine whether they have a copy of a requested block.
- DSnooping-based protocols are more popular than directory-based ones.
5Which of the following are correct about common protocols to maintain cache coherence?
- AThe write broadcast protocal consumes too much bandwidth and is therefore less commonly used.
- BThe write invalidate protocal is less efficient than the write-broadcast protocal and is therefore less commonly used.
- CIn the write-broadcast protocol, each processor writing to a shared data must update all the cached copies of the data.
- DIn write-invalidate protocols, before each processor is allowed to write a data, ensure that it has exclusive access to a data by invalidating copies in other caches.
6Which of the following are correct about a snoop-based write-invalidate protocol?
- AThe last level shared cache mainains a directory of all the shared data that reside in caches.
- BEach cache block includes a valid bit, a dirty bit, add a state bit to track whether it is shared,
- CWhen writing to a block with the shared bit set, the cache generates an invalidation on the bus. The state of the owner’s cache block is then changed from shared to unshared (or exclusive).
- DEvery bus transaction must check the cache-address tags, which could potentially interfere with processor cache accesses, unless the shared tags for snoop accesses are duplicated.
- EIf another processor later requests an exclusive cache block, the owner of the block sees the request and marks the block back into being shared again.
7Consider an 8-processor multicore where each processor has its own L1 and L2 caches, and snooping is performed on a shared bus among the L2 caches. Assume the average L2 request, whether for a coherence miss or other miss, is 15 cycles. Assume a clock rate of 3.0 GHz, a CPI of 0.7, and a load/store frequency of 40%. If our goal is that no more than 50% of the L2 bandwidth is consumed by coherence traffic, what is the maximum coherence miss rate per processor?
- A0.8%
- B0.73%
- C7.3%
- D8%
8Which of the following correctly categorize thread-level parallelism (TLP)?
- ATLP implies the existence of multiple program counters and is exploited primarily through MIMDs.
- BIt can be used to support parallel processing, where a tightly coupled set of threads collaborating on a single task;
- CIt supports parallelism only from a single application.
- DIt can be used to support request-level parallelism, which executes multiple, relatively independent processes that may originate from one or more users
- EIt is supported by multiprocessors, which are tightly coupled processors whose coordination and usage are controlled by a single operating system and who share a single address space.
9Which of the following correctly categorize MIMD multiprocessor architectures designed to support TLP?
- AA single physical memory is shared among all processors.
- BThey supports only small-scale parallelism, typically using at most hundreds of processor cores.
- CThey sometimes include multiple computations connected through loose internet communications.
- DTheir multiprocssor systems include both single-chip systems with multiple cores, known as multicore, and computers consisting of multiple chips, each of which is typically a multicore.
10Which of the following summarize existing classes of shared-memory multiprocessors?
- ADistributed shared memory or NUMA (non-uniform memory access) systems, which consist of multiprocessors on multiple chips with physically distributed memory and non-uniform access lalency to local vs. remote memory.
- BWarehouse computing servers, which include a large number of servers in data centrers.
- CSymmetric multiprocessors (SMPs), typically with 32 or fewer cores, all of which share a single centralized memory that all processors have uniform access latency.
- DMulti-computer systems, which include relatively independent multiprocessors loosely connected with slow network.
11Which of the following are required to take advantage of an MIMD multiprocessor with n processors?
- AThe amount of inter-thread synchronization and communication must be sufficiently small.
- BThere must be at least n software threads or processes to execute;
- CThe amount of computation assigned to a thread, called the grain size, must be sufficiently large.
- DThere must be sufficient instruction-level parallelism within each thread of execution
12Which of the following summarize key challanges and solutions in efficient parallel processing?
- ALong remote access latency can be attacked with local caches in architectures.
- BThe relatively high cost of communications, which is a main source of overhead in TLP.
- CParallelism limitations in software can be attached with new better algorithms that offer more concurrency.
- DTLP is expect to attain linear speedups with existing technologies.
- EInsufficient parallelism available in software programs.
13Example: Suppose you want to achieve a speedup of 80 with 100 processors. What fraction of the original computation can be sequential? (TB Page 374).
- A25%
- B0.25%
- C2.5%
- D0.025
14Suppose we have an application running on a 100-processor multiprocessor, and assume that application can use 1, 50, or 100 processors. If we assume that 95% of the time we can use all 100 processors, how much of the remaining 5% of the execution time must employ 50 processors if we want a speedup of 80? (Page 375)
- A5.2
- B5
- C4.8%
- D4.5
15Continuing from the above example,
how much of the remaining 5% of the execution time can be run on a single thread?- A0.3
- B0.2
- C0.1
- D0.4
16What are the pros and cons of the SMP design with snooping cache coherence?
- AIt requires communication with all caches on every write to shared data.
- BIt requires communication with all caches on every cache miss
- CIt requires overly high memory bus and interconnection bandwidth for large number of processors
- DIt separates the traffic between local data and remote data accesses.
- EIt does not require any centralized data structure to track the states of the caches
17What are the main ideas of distributed directory-based cache coherence?
- AIt allows the coherence protocol to avoid broadcast.
- BA distributed directory retains that the sharing status of a block is always in a single known location.
- CIt allows the coherence protocol to avoid interprocessor communication.
- DIt maintains an entry for each memory block regarding what other nodes may be caching the block,
18What are the pros and cons of the DSM design with directory-based cache coherence?
- AIt uses a global directory to track the state of every block that may be cached.
- BIt separates local memory traffic from remote memory traffic
- CIt uses a directory per multi-core processor to track the state of every block locally cached.
- DIt eliminate the need to broadcast on every cache miss.
- EIt reduces bandwidth demands on the memory system and on the interconnection network.
19Which of the following correctly categorize thread-level parallelism (TLP)?
- ATLP implies the existence of multiple program counters and is exploited primarily through MIMDs.
- BIt can be used to support parallel processing, where a tightly coupled set of threads collaborating on a single task;
- CIt supports parallelism only from a single application.
- DIt can be used to support request-level parallelism, which executes multiple, relatively independent processes that may originate from one or more users
- EIt is supported by multiprocessors, which are tightly coupled processors whose coordination and usage are controlled by a single operating system and who share a single address space.
20Which of the following correctly categorize cache coherence misses?
- AThe true sharing misses triggered by write accesses by other processors to shared data.
- BThe false sharing misses triggered by a data item being adjacent to shared data written by other processors.
- CThe compulsary cache misses when a shared data item is accessed first.
- DThe conflict misses when shared data reside in the caches of multiple processors.
21What are the valid states of a cache block in a directory-based coherence protocal?
- AUncached: No node has cached a copy of the block.
- BModified: exactly one node has cached a copy of the block, and it has written the block, so the memory copy is out of date.
- COwned: exactly one node has cached a copy of the block, and it has not modified the block.
- DShared: One or more nodes have cached the block, and the values in memory and all the caches are up to date.
22What are the possible types of messages among nodes to maintain coherence (Fig 5.19, page 407)?
- AFetch/invalidate: fetch the block at address A and send it to its home directory; change the state of A in the remote cache to shared (in the case of fetch) or invalidate the block in the caches (in the case of invalidate).
- BRead/Write hits: read or write data that reside in local cache.
- CInvalidate: invalidate all shared copies of data at address A.
- DData value/write-back: return a data value from the home memory or write back a data value for address.
- ERead/write miss: a node P has a read or write miss at address A; request data and make P a read sharer or the exclusive owner.
23Which of the following summarize how software typically support synchronization?
- AHardware supplies an uninterruptible instruction or instruction sequence capable of atomically retrieving and changing a value.
- BSystem-level software supplies abstractions for user-level software to synchronize and communicate with each other
- CHardware supplies abstractions for software to communicate with each other
- DUser-level software implement abstractions that rely on hardware-supplied synchronization instructions.
24Which of the following are typical hardware atomic instructions for supporting synchronization?
- Atest-and-set, which tests a value and sets it if the value passes the test.
- Bfetch-and-increment, which returns the value of a memory location and atomically increments it.
- CConditional store, which stores a value into an address only when a user-defined condition is true.
- Datomic exchange, which interchanges a value in a register for a value in memory
25Alternative to a single atomic memory operation, synchronization can be supported by using a pair of load and store operations, where
- Ahe number of instructiosn between the load-reserve and store-conditional must be kept small and bounded by a small constant.
- BThe store operation succeeds only if the reservation has not been broken by other writes.
- CThe load operation reserves a memory address while loading its content.
- DOnly register-to-register instructions are allowed in between the load and store pair.
- EIf the store fails, it overwrites the given value register with a non-zero; otherwise, it overwrites the register with zero.
26What are the advantages of using cache coherence to support locking?
- AIt can benefit from temporal locality in locking.
- BIt can benefit from spatial locality in locking.
- CIt avoids memory access in the locking process.
- DIt allows the user process to spin on a cached lock instead of requiring a global memory access on each locking attempt.
27What question does the memory consistency model address?
- AIt addresses the question of how consistent memory must be when multiple processors read/write the memory.
- BIt addresses the question of which orderings among instructions are allowed when then access memory.
28Which of the following is correct about sequential consistency model?
- AIt require a processor to delay the completion of any memory access until all the invalidations caused by that access are completed.
- BIt allows memory accesses from different processors to be arbitrarily interleaved.
- CIt makes the execution easy to understand but potentially reduces performance.
- DIt requires all memory accesses by the same processor to be executed in order.
29Which of the following is correct about the relaxed consistency model?
- AIt ensures that a synchronized program behaves as though the processor were sequentially consistent.
- BIt avoids data races among processors.
- CIt allows reads and writes to complete out of order;
- DIt uses synchronization operations to enforce ordering;
30What are the variety of relaxed consistency models?
- AThe weak ordering (or release consistency model) does not require any ordering among operations unless special synchronization operations are used before/after the operations.
- BThe partial store ordering does not require wrote operations to be ordered.
- CAll consistency models allow some multi-process programs to execute correctly without special synchronizations.
- DThe total store ordering model (or processor consistency model) requires ordering among write operations while allowing write operations to be completed out-of-order regarding read operations.
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- Test sobre Sin título, creado por Tyler Young el 10/05/2021.
- Autor
- Tyler Young
- Idioma
- English
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