Test
NTEN 111 - Midterm 1 Study Guide
Preguntas del test (83)
1Which of the following problems would NOT being identified during POST?
- Amemory failure
- Bbad monitor
- Cbad video card
- Dfaulty CPU
2In the figure below, Item D is the _______.
- Asystem board connections for IDE and floppy drives
- BDIMM slots
- CP1 power connection on the system board
- DPCI local bus slots
3The correct order of the boot process is:
- APOST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
- BPOST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
- CPOST, OS configures the system and completes loading, User is able to execute application software
- DPOST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS
4What's the first thing the Startup BIOS looks for on a hard drive during boot up?
- ADOS Boot Record
- BMaster Boot Record Correct
- CNT Boot Record
- DPiece of Pie
5POST stands for:
- Apartial operating system test
- BPower-off self test
- CPower-on self test
- DPre-operational system test
- ENone of the above
6Which of the following is NOT a motherboard form factor:
- AATX
- BMicro-PTX
- CLPX
- DBTX
- EAT
7Which statement is NOT true about CMOS chips:
- AThey maintain their settings long after you remove the CMOS battery
- BThey generally hold between 64 bytes and 512 bytes of memory
- CThey are sometimes referred to as NVRAM
- DThey contain resource settings for plug-and-play devices in the ESCD
- EThey contain the Real Time Clock that holds PC's time and date settings
8How many of the following components are part of the CPU?
• ALU
• Real Time Clock
• branch predictor
• Registers
• Program Counter- A1
- B2
- C3
- D4
- E5
9Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?
- ADoubler and Tripler clocks
- BDerived System Clocks
- CMultiplier and Divider Clocks
- DFrequency Multiplexers
10Which term is commonly used to reference the process of division and
multiplication of the system clock to achieve the desired frequency?- ADoubler and Tripler clocks
- BDerived System Clocks
- CMultiplier and Divider clocks
- DFrequency Multiplexers
11Secondary cache, also called ______ cache, may be located either in the
CPU cartridge or on the system board near the CPU.- AL1
- BL2
- CL3
- DL4
12How many of the following items are true regarding cache?
◦ Cache uses DRAM with is faster that SRAM (found in main memory)
◦ Cache is not always found in the CPU
◦ Cache is designed as temporary storage for the CPU
◦ The size of cache is matched to be equal to the amount of main memory in
the computer- A0
- B1
- C2
- D3
- E4
13Early Pentium CPUs are said to have multi-processing capabilities because they ____________
- ACan process data coming in while sending data out
- BHave the ability to exist with other processors
- CUse multiple registers
- D Contain two Arithmetic Logic Units Correct
14Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
- AL4
- BL3
- CL2
- D L1
15Different speeds for computer components are achieved by using what is called ___________.
- AFrequency Multiplexers
- B Multiplier and Divider clocks
- CDerived System Clocks
- DDoubler and Tripler clocks
16Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.
- A I/O Controller Hub
- BISA bus
- CGraphics Memory Controller Hub
- DSouth Bridge
17The amount of addressable memory is determined by the size of the address bus.
- AVerdadero
- BFalso
18The Multiplier is the term used to describe the ________________
- Athe ratio of the Backside Bus speed to the Memory Bus speed
- B the ratio of the Backside Bus speed to the CPU operating speed
- Cthe ratio of the CPU operating speed to the Front Side Bus speed
- Dthe ratio of the PCI bus speed to the Memory Bus speed
19The front side bus connects the CPU to the ______.
- Acoprocessor
- BL1 cache
- Csystem clock
- Dmemory bus
20A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump
- AControl Unit
- BBranch Predictor
- CHyper-Threading Technology
- DCache
21A unit that controls the operations of all components in the processor and executes conditional instructions
- Acontrol unit
- BInstruction Register
- CBranch Predictor
- DALU
22Allows access to the hard disk drive, USB ports and other I/O devices
- ACache
- BProgram Counter
- CNorth Bridge
- DSouth Bridge
23Allows access to the RAM and video card
- ANorth Bridge
- BSouth Bridge
- CWest Bridge
- DEast Bridge
24A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel
- ACache
- BArithmetic Logic Unit
- CHyper-Threading Technology
- DSuperscalar Architecture
25An internal memory location that contrains the instruction that is to be executed.
- ACache
- BInstruction Register
- CBranch Predictor
- DSouth Bridge
26The part of the CPU that processes arithmetic and logical instructions
- AFloating Point Unit
- BArithmetic Logic Unit
- CMultiplier Bus
- DDivisor Programming Unit
27An internal memory location that contains the address of the next instruction to be executed
- ACounting Register
- BAddress Bus Architecture
- CAddress Memory Unit
- DProgram Counter
28Used as temporary storage for the CPU
- ARAM
- BROM
- CCache
- DHard Disk Drive
29The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.
- ADMA Controller
- BIRQ Controller
- CChipset
- DSuper I/O
30Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)
- AISA
- BSystem
- CAGP
- DMemory
- EVESA-Local Bus
- FPCI
31With 486 and higher CPUs, the cache controller is ________.
- Aattached to the CMOS chip
- Bnot required, as the CPU itself controls the cache
- Choused on the system board
- Dembedded in the CPU chip
32Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.
- AFast Bridge
- BICH
- CNorth Bridge
- DSouth Bridge
33Which of the following items relieves the CPU of processing traffic to
and from all the buses and controllers on the system board?- AIRQ Controller
- BChipset
- CDMA Controller
- DSuper I/O
34The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.- ASouth Bridge
- BNorth Bridge
- CICH
- DEast Bridge
- EWest Bridge
35How many of the following buses connect to the GMCH in the
Accelerated Hub Architecture Chipset?
•PCI • System
• Memory • AGP
• ISA • VESA-Local Bus- A1
- B2
- C3
- D4
- E5
36Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.
- A356
- B504
- C768
- D943
37A SCSI chain must be terminated either by a passive, active or forced perfect terminator.
- AVerdadero
- BFalso
38With IDE drives, the OS executes the remainder of the format process. This is known as a _____.
Select one:- Alow level format
- Bhigh-level format
- Cpartition
- Dpart
39Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.
- AVerdadero
- BFalso
40Which SCSI ID would usually be used for Hard Drives?
- A0
- B2
- C4
- D7
41In a process called _____, track and sector markings are written on the hard drive at the factory.
- Ahigh-level formatting
- Blow level formatting
- Cpartitioning
- Dparking
42IDE drives use a _____-pin cable.
- A34
- B40
- C50
- D68
43LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.
- AVerdadero
- BFalso
44What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?
- AParallel ATA
- BSerial ATA
- CSynchronous ATA
- DSingle Mode ATA
45Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.
- AVerdadero
- BFalso
46Zone Bit Recording means ___________________
- Athe number of sectors/track vary depending on the location of the track.
- Bthe tracks are arranged so the same number of sectors are used for all tracks.
- Ceach bit is recorded one zone at a time
- Da type of logical method of addressing larger capacity drives
47Serial ports transmit data one byte at a time.
- AVerdadero
- BFalso
48Which of the following is NOT a type of parallel port?
- ASPP
- BEPP
- CECP
- DEDP
49Parallel ports transmit data in parallel, _____ bit(s) at a time.
- A1
- B2
- C4
- D8
50When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.
- ANormal
- BLBA
- CCHS
- DECHS
51Which of the following is true about SCSI vs EIDE?
- AEIDE is harder to set up than SCSI
- BSCSI is faster and more expensive
- CEIDE is faster and more expensive
- DSCSI is more popular than EIDE
52The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?
- A504 MB
- B7.88 Gbits
- C128 GB
- D7.88 GB
53In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.
- Aadapter
- BROM bios
- CCMOS chip
- Dcontroller
54The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.
- Aactuators
- Bheads
- Cplatters
- Dspindles
55A null-modem cable can be used to directly connect two ____ devices.
- ADTE
- BDCE
- CDCA
- DDMA
56Which statement is NOT true about CMOS chips:
- AThey maintain their settings long after you remove the
CMOS battery - BThey generally hold between 64 bytes and 512 bytes of
memory - CThey are sometimes referred to as NVRAM
- DThey contain resource settings for plug-and-play devices in
the ESCD (Extended System Configuration Data) area - EThe contain the Real Time Clock that holds the PC’s time
and date settings
- AThey maintain their settings long after you remove the
57The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.- ASouth Bridge
- BNorth Bridge
- CICH
- DEast Bridge
- EWest Bridge
58Parallel ports are only able to transmit data in one direction at any given
time.- AVerdadero
- BFalso
59Synchronous memory requires an external clock signal while
Asynchronous does not.- AVerdadero
- BFalso
60How many of the following statements are true?
◦ DRAM is always faster that SRAM
◦ SRAM is lower cost that DRAM
◦ Both DRAM and SRAM are available in synchronous and asynchronous forms
◦ Both SRAM and DRAM retains values when the power is off- A0
- B1
- C2
- D3
- E4
61How many of the following statements are true?
◦ DRAM does not require refreshing to hold data
◦ SRAM allows for faster data access that DRAM
◦ SRAM costs more than DRAM per byte
◦ SRAM and DRAM memory cells are the same physical size per byte- A0
- B1
- C2
- D3
- E4
62How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors- A0
- B1
- C2
- D3
- E4
63How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors- AEven
- BOdd
64Which BUS version is set to replace AGP?
- APCIe
- BISA
- CInfiniband
- DPCI-X
65With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.
- AVerdadero
- BFalso
66Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.
- AVerdadero
- BFalso
67What kind of Parity checking is being used if the following byte of data and it's parity bit are correct:
Value: 1011 0111 Parity Bit: 1- Aeven
- Bequal
- Codd
- Dbalanced
68Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.
- APRAM, DRAM
- BSRAM, DRAM
- CDRAM, SRAM
- DSRAM, PRAM
69What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?
- ARam Timing Detect
- BAuto-Timing Detect
- CSerial Presence Detect
- DMemory Alert
70Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.
- AVerdadero
- BFalso
71You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?
- A1.6GB/s
- B2.1GB/s
- C3.2GB/s
- D1.06GB/s
72One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.
- Achecksum
- Bbit parity
- CESCD
- DPRAM
73What type of bus is displayed in the figure below
- A16-bit ISA
- BVESA
- C8-bit ISA
- DPCI
74The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus.
(HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)- A6,3
- B3,6
- C5,3
- D5,4
75Which of the following is a list of expansion bus types ?
- AMCA, PCI, Memory
- BISA, EISA
- CISA, PCD, AGD
- DPCI, DIMM, SIMM
76The ______ ISA bus was so named because it had only an eight-bit data path.
- A4-bit
- B8-bit
- C16-bit
- D32-bit
77ECC may be present on DIMM module, and correct single bit errors when possible.
- AVerdadero
- BFalso
78DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.
- AVerdadero
- BFalso
79Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.
- Aeven
- Bequal
- Codd
- Dbalanced
80All data stored in _____ is lost when the power is turned off.
- APRAM
- BRAM
- CROM
- DCMOS
81On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)
- A2.1 GB/s
- B1.6 GB/s
- C500 MB/s
- D3.2 GB/s
82The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.
- AS-100
- B8-bit ISA
- C16-bit ISA
- DEISA
83ECC RAM differs from parity and nonparity RAM in that it can ______.
- Aretain data when the power is removed
- Bdetect errors
- Cautomatically save data to the hard drive
- Ddetect and potentially correct errors
Información
- Descripción
- Preperation for NTEN 111 at Okanagan College (2015, Berg)
- Autor
- j.salvino
- Idioma
- English
- Visitas
- 39
- Etiquetas
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