6752676
Descripción
Test por Zim Brightwood, actualizado hace más de 1 año
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Creado por Zim Brightwood
hace más de 7 años
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Pregunta 1
Pregunta
Throughput is
Respuesta
-
the rate at which instructions leave the pipeline
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total time it takes an instruction to be processed by a stage
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the rate at which instructions move to the next register
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total time it takes an instruction to be processed by the entire pipeline
Pregunta 2
Pregunta
Latency is
Respuesta
-
total time it takes an instruction to be processed by the entire pipeline
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the rate at which instructions leave the pipeline
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the rate at which instructions move to the next register
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total time it takes an instruction to be processed by a stage
Pregunta 3
Pregunta
Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
Respuesta
-
Throughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
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Throughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
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Throughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up
Pregunta 4
Pregunta
Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
Respuesta
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between each stage
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after each stage
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before each stage
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inputs for that stage
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outputs for that stage
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inputs for the next stage
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in parallel
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sequentially
Pregunta 5
Pregunta
And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
Respuesta
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in flight
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executing
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latent
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active
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retired
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finished
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complete
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ready
Pregunta 6
Pregunta
The pipeline instructions are executed in order
Respuesta
- True
- False
Pregunta 7
Pregunta
Instruction-level parallelism exists between a pair of instructions if
Respuesta
-
their execution order does not matter
-
their execution order matters
Pregunta 8
Pregunta
The pipeline requires some parallelism
Respuesta
- True
- False
Pregunta 9
Pregunta
Dependencies exist if execution order doesn't matter
Respuesta
- True
- False
Pregunta 10
Pregunta
Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
Respuesta
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B reads value written by A Example: a = 1; b = a;
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B write to visible location written by A Example: a = 1; a = 2;
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B write to a location read by A Example: b = a; a = 1;
Pregunta 11
Pregunta
Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
Respuesta
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B write to visible location written by A Example: a = 1; a = 2;
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B reads value written by A Example: a = 1; b = a;
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B write to a location read by A Example: b = a; a = 1;
Pregunta 12
Pregunta
Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
Respuesta
-
B write to a location read by A Example: b = a; a = 1;
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B reads value written by A Example: a = 1; b = a;
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B write to visible location written by A Example: a = 1; a = 2;
Pregunta 13
Pregunta
[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
Respuesta
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Expressing
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Adding
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Mechanizing
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Conflating
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Eating
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Exploiting
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Removing
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Smelling
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Tangential Execution
Pregunta 14
Pregunta
A pipeline hazard exists when
Respuesta
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the processor's execution would violate a data or control dependency
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the processor's execution would support a data or control dependency
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the processor's execution would cause a data or control dependency
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the processor's execution would execute a data or control dependency
Pregunta 15
Pregunta
We should detect pipeline hazards
Respuesta
- True
- False
Pregunta 16
Pregunta
Stalling is one way to handle pipeline hazards
Respuesta
- True
- False
Pregunta 17
Pregunta
A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle.
A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.
Respuesta
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pipeline stall
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pipeline bubble
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pipeline hazard
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pipeline stage
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pipeline overhead
Pregunta 18
Pregunta
The only data hazards in the Y86 Pipeline are causal hazards on register file
Respuesta
- True
- False
Pregunta 19
Pregunta
The only control hazards in the Y86 Pipeline are conditional jumps
Respuesta
- True
- False
Pregunta 20
Pregunta
To prevent a data hazard by stalling, we can
Respuesta
-
read registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
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read registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
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read registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired
Pregunta 21
Pregunta
How would we resolve a conditional jump control hazard by stalling?
Respuesta
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stall fetch until jump exits execute
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stall execute until jump exits decode
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stall fetch and execute until jump exits decode
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stall fetch, decode, and execute until jump exits memory
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stall fetch, decode, execute, and memory until jump exits write back
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just stall everything after fetch indefinitely and go finish off a bottle of wine in one go
Pregunta 22
Pregunta
How would we resolve a return control hazard by stalling?
Respuesta
-
stall fetch until return exits memory
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stall decode until return exits memory
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stall fetch and decode until return exits memory
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stall fetch, decode, and execute until return exits memory
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stall fetch, decode, execute, and memory until return exits memory
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return to cpsc313 in the summer after you fail this midterm
Pregunta 23
Pregunta
Check all the statements that are true about the pipeline-control module
Respuesta
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it's a hardware component separate from the 5 stages
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examines values across every stage
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decides whether stage should stall or bubble
Pregunta 24
Pregunta
Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
Respuesta
- True
- False
Pregunta 25
Pregunta
Where does data forwarding forward its data to?
Respuesta
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D
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W
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M
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E
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F
Pregunta 26
Pregunta
Where does data forward forward its data from?
Respuesta
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W - new value from memory or ALU
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M - new value read from memory or from ALU
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E - new value from ALU
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D - new value from registers
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F - new value from PC determined instruction
Pregunta 27
Pregunta
Which of these are data hazards?
Respuesta
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register-register hazard
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load-use hazard
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register-memory hazard
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memory-memory hazard
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use-use hazard
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load-load hazard
Pregunta 28
Pregunta
Which of these is a register-register hazard?
Respuesta
-
irmovl $1, %eax addl %eax, %ebx
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irmovl $1, %ecx addl %eax, %ebx
Pregunta 29
Pregunta
How do we handle a register-register hazard with data forwarding?
Respuesta
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forward to D from E, M, or W
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forward to F from E, M, or W
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stall one cycle, then forward to D from E, M, or W
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stall one cycle, then forward to F from D, E, M, or W
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stall one cycle, then forward to F from E, M, or W
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forward to F from D, E, M, or W
Pregunta 30
Pregunta
Which of these is a load-use hazard?
Respuesta
-
mrmovl (esi), %eax addl %eax, %ebx
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rmmovl %eax, (esi) addl %eax, %ebx
Pregunta 31
Pregunta
How would we handle a load-use hazard?
Respuesta
-
Stall use one cycle, forward to D from M or W
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Stall use one cycle, forward to D from E or M
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Stall use one cycle, forward to E from D, M, or W
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Stall use one cycle, forward to E from M or W
Pregunta 32
Pregunta
Jump prediction is not suitable for resolving conditional-jump hazards
Respuesta
- True
- False
Pregunta 33
Pregunta
We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
Respuesta
-
E
-
D
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M
-
W
Pregunta 34
Pregunta
valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
Respuesta
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not taken
-
taken
Pregunta 35
Pregunta
When a mis-predicted jump is in M, what should we do?
Respuesta
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shootdown D and E to prevent them from doing damage
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shootdown F and D to prevent them from doing damage
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shootdown M and W to prevent them from doing damage
Pregunta 36
Pregunta
The homework in this course is much too long
Respuesta
- True
- False
Pregunta 37
Pregunta
We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
Respuesta
- True
- False
Pregunta 38
Pregunta
We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
Respuesta
- True
- False
Pregunta 39
Pregunta
In regards to static jump prediction, what could the compiler know?
Respuesta
-
a jump's taken tendency
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for loops, it can decide to use a continue condition or exit condition
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for if statements it might be able to spot error tests
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what it sees in the program text
Pregunta 40
Pregunta
The compiler cares about the ISA's jump predictions
Respuesta
- True
- False
Pregunta 41
Pregunta
How do we optimize handling the return hazard?
Respuesta
-
Keep a stack of return addresses for future use
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Guess the return address based on the value in predPC
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Guess the return address based on the value in PC
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Guess the return address based on the valP in D
Pregunta 42
Pregunta
Y86 has indirect jumps
Respuesta
- True
- False
Pregunta 43
Pregunta
Indirect jumps are needed for polymorphic dispatch
Respuesta
- True
- False
Pregunta 44
Pregunta
CPI =
Respuesta
-
totalCycles / instructionRetiredCycles
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instructionRetiredCycles / totalCycles
Pregunta 45
Pregunta
What are the tendencies of deeper pipelines?
Respuesta
-
reduce clock period
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increase CPI
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makes stalling harder to avoid
Pregunta 46
Pregunta
Which of these are attributes of super-scalar?
Respuesta
-
multiple pipelines that run in parallel
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issue multiple instructions on each cycle
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instructions execute in parallel and can even bypass each other
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if I shut my eyes tight enough, will the midterm disappear?
Pregunta 47
Pregunta
What does hyper-threading consist of? (Only one of the following is correct)
Respuesta
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OS loads multiple runnable threads into CPU, usually from the same process
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CPU does fast switching between threads to hide memory latency
Pregunta 48
Pregunta
What is multi-core?
Respuesta
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multiple CPUs per chip, each pipelined, super-scalar, etc
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CPU's execute independent threads from possibly different processes
Pregunta 49
Pregunta
How could Mike do this to us?
Respuesta
-
Sadism
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Also sadism
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And sadism
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All of the above
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