Test
CSA Last p1
Preguntas del test (69)
1The main computer that stores the files that can be sent to computers that are
networked together is...?:- AClip art
- BMother board
- CPeripheral
- DFile server
2Addressing mode used in instruction: add r1, r2, r3 is?
- ARegister
- BIndirect
- CBase
- DImmediate
3In generic microprocessor instruction time is…?
- AExactly same as machine cycle time
- BShorter than machine cycle time
- CLarger than machine cycle time
- DTen times machine cycle time
4Hardware devices that are not part of the main computer system and are often added later to the system?
- APeripheral
- BClip art
- CHighlight
- DExecute
5Using a(n) _____ protocol, the sender and the receiver are synchronized by a
signal called a clock- Asynchronous
- Basynchronous
- Canalogue
- Dblock
6The bandwidth of a(n) _____ signal is usually measured in bits per second.
- Avideo
- Bdigital
- Csatellite
- Danalog
7A communications _____ is a physical path or frequency for a signal
transmission.- Aband
- Bchannel
- Cprotocol
- Dbridge
8Which of the following terms represents the transmission capacity of a
communications channel?- AIndexing
- BFrequency
- CBandwidth
- DResolution
9How many parts of Memory Hierarchy?
- A5
- B4
- C2
- D3
10In Memory Hierarchy, at the Outboard storage which of the following are
included:- ACache
- BMain memory
- CMagnetic tape
- DMagnetic disk
11In Memory Hierarchy, at the Off-line storage which of the following are included:
- ACache
- BMagnetic disk
- CMagnetic tape
- DMain memory
12In Memory Hierarchy, at the Inboard memory which of the following are
included:- AMain memory
- BMagnetic disk
- CMagnetic tape
- DOptical disk
13Cache Design has these properties?
- ASize, block size, mapping function, replacement algorithm, write policy
- BSize, search function, write function, read policy, vector algorithm
- CSize, mapping algorithm, vector function, write policy, replacement function
- DSize, blocking algorithm, search function, replacement vector, read policy
14Three techniques are possible for I/O operations:
- AProgrammed I/O, Interrupt-driven I/O, Direct memory access(DMA)
- BObject-oriented I/O, Design I/O, Usable I/O
- CMachine I/O, Architecture I/O, Hardware I/O
- DControl I/O, Status I/O, Transfer I/O
15How many principles has Deadlock?
- A3
- B5
- C2
- D6
16Which of the following principles has Deadlock?
- APrevention, Avoidance, Detection
- BExecution, Association, Starvation
- CExclusion, Avoidance, Starvation
- DStarvation, Detection, Exclusion
17Much of the work in security and protection as it relates to operating systems
can be roughly grouped into four categories?- AAvailability, confidentiality, data integrity, authenticity
- BSafety, accountability, reliability, density
- CUsability, integrity, confidentiality, reliability
- DFlexibility, availability, accountability, authenticity
18The central themes of operating system design are all concerned with the
management of processes and threads?- AMultiprogramming, multiprocessing, distributed processing
- BMultitasking, multiprogramming, multithreading
- CMultiprocessing, uniprocessing, multitasking
- DMultithreading, distributed processing, uniprocessing
19Can you solve the Dining Philosophers’ Problem using monitors?
- Ayes
- Bno
20Assembly line operation is also called as?
- ASuperscalar operation
- Bpipelining process
- CVon-Neumann cycle
- DNone of the mentioned
21The CISC stands for?
- AComputer Instruction Set Compliment
- BComplete Instruction Set Compliment
- CComputer Indexed Set Components
- DComplex Instruction Set Computer
22The secondary effect that results from instruction scheduling in large code
segments is called ____?- AAggressive instruction
- BCorrelating predictors
- CRegister predictors
- DRegister pressure
23How many instructions can be implemented in MIPS?
- A2 clock cycles
- B3 clock cycles
- C4 clock cycles
- D5 clock cycles
24What do you call the given statement as: “The number successful accesses to
memory stated as a fraction.”- AHit rate
- BMiss rate
- CSuccess rate
- DAccess rate5 clock cycles
25Of the following, identify the memory usually written by the manufacturer.
- ARAM
- BDRAM
- CROM
- DCache memory
26The Sun micro systems processors usually follow _____ architecture
- ACISC
- BISA
- CULTRA SPARC
- DRISC
27The iconic feature of the RISC machine among the following are
- AReduced number of addressing modes
- BIncreased memory size
- CHaving a branch delay slot
- DAll of the above
28Pipe-lining is a unique feature of _
- ARISC
- BСISC
- CIANA
- DISA
29Performance of a machine is determined by:
- AInstruction count, Clock cycle time, Clock cycles per instruction
- BInstruction count, Clock cycle time, Correlating predictors
- CClock cycle time, Correlating predictors, Aggressive instruction
- DClock cycle time, Clock cycles per instruction, Correlating predictors
30What do you call the given statement as for type of memory?: “High density, low
power, cheap, slow, need to be “refreshed” regularly”- ADRAM
- BSRAM
- CCISC
- DRAM
- EROM
31Definition of Block:
- Aminimum unit that is present or not present
- Blocation of block in memory
- Cpercentage of time item not found in upper level
- Dmemory closer to processor
- Etime to access upper level
32Definition of Block address:
- Aminimum unit that is present or not present
- Blocation of block in memory
- Cpercentage of time item not found in upper level
- Dmemory closer to processor
- Etime to access upper level
33What is the total number of writes?
- A196
- B784
- C512
- D1024
34What is the total number of writes that miss in the cache?
- A588
- B196
- C25%
- D12,5%
35What is the total number of writes that hit in the cache?
- A588
- B784
- C12,5%
36Suppose that we want to enhance the processor used for Web serving. The new
processor is 10 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?- A≈ 1.86
- B≈ 1.96
- C≈ 1.56
- D1.30
37Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?- A≈ 1.25
- B≈ 1.96
- C≈ 1.56
- D1.30
38Suppose that we want to enhance the processor used for Web serving. The new
processor is 5 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 50% of the time and is waiting for I/O 50% of the time, what is the
overall speedup gained by incorporating the enhancement?- A≈ 1.86
- B≈ 1.96
- C≈ 1,67
- D1.30
39Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 30% of the time and is waiting for I/O 70% of the time, what is the overall speedup gained by incorporating the enhancement?- A≈ 1.86
- B≈ 1.18
- C≈ 1.56
40What is a RISC?
- AReduced Instruction Set Computer
- BRational Interruptible Security Computer
- CResearch Interconnect Several Computer
41When single-processor performance improvement has dropped?
- A2003
- B2004
- C2002
42How much in percentage single-processor performance improvement has dropped to less than?
- A22
- B11
- C33
43What is the RLP?
- AResearch Level Parallelism
- BRandom Level Parallelism
- CRequest Level Parallelism
44How many classes of computers classified?
- A7
- B3
- C5
45Which distance of price has Clusters/warehouse-scale computers?
- A100 000 - 200 000 000 $
- B5 000 – 10 000 000 $
- C100 – 100 000 $
46What is the PMD in computer classes?
- APercentage map device
- BPowerful markup distance
- CPeak maze development
- DPersonal mobile device
47The Application of Brokerage operations how many cost of downtime per hour?
- A8 870 000 $
- B6 450 000 $
- C7 550 000 $
48What is the Vector Architectures and Graphic Processor Units (GPUs) -
- AExploit data-level parallelism by applying a single instruction to a collection of data in
parallel. - BExploits data-level parallelism at modest levels with compiler help using ideas like pipelining
and at medium levels using ideas like speculative execution. - CExploits parallelism among largely decoupled tasks specified by the programmer or operating
system.
- AExploit data-level parallelism by applying a single instruction to a collection of data in
49What is the Thread Level Parallelism -
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled
hardware model that allows for interaction among parallel threads. - BExploits parallelism among largely decoupled tasks specified by the programmer or operating
system. - CExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled
50What is the Request Level Parallelism:
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware
model that allows for interaction among parallel threads. - BExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- CExploits parallelism among largely decoupled tasks specified by the programmer or
operating system.
- AExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware
51What is the Instruction Level Parallelism:
- AExploits data-level parallelism at modest levels with compiler help using ideas like
pipelining and at medium levels using ideas like speculative execution. - BExploits parallelism among largely decoupled tasks specified by the programmer or operating
system. - CExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- AExploits data-level parallelism at modest levels with compiler help using ideas like
52What is the MISD one of the categories of computers?
- AMultiple Instructions Streams, Single Data Stream
- BMultiple Instruction Streams, Multiple Data Streams
- CMultiple Instruction Streams, Set Data Stream
53How many elements in Trends of Technology?
- A3
- B4
- C5
54How many elements of the Instruction Set Architecture (ISA):
- A5
- B6
- C7
55What is a ARF:
- AArchitectural Register File
- BArchitecture Relocation File
- CArchitecture Reload File
- DArchitectural Read File
56What is a ROB?
- AReorder Buffer
- BRead Only Buffer
- CReload Buffer
- DRecall Buffer
57What is a FSB?
- AFinished Store Buffer
- BFinished Stack Buffer
- CFinished Stall Buffer
- DFinished Star Buffer
58What is a PRF?
- APhysical Register File
- BPending Register File
- CPipeline Register File
- DPure Register File
59What is a SB?
- AScoreboard
- BScorebased
- CScaleboard
- DScalebit
60How many stages used in Superscalar (Pipeline)?
- A5
- B4
- C6
61What is about Superscalar means “F-D-X-M-W”?
- AFetch, Decode, Execute, Memory, Writeback
- BFetch, Decode, Instruct, Map, Write
- CFetch, Decode, Excite, Memory, Write
- DFetch, Decode, Except, Map, Writeback
62Speculating on Exceptions “Prediction mechanism” is -
- AExceptions are rare, so simply predicting no exceptions is very accurate
- BExceptions detected at end of instruction execution pipeline, special hardware for various exception
types - COnly write architectural state at commit point, so can throw away partially executed instructions after
exception - Dnone
63Speculating on Exceptions “Check prediction mechanism” is -
- AExceptions detected at end of instruction execution pipeline, special hardware for various
exception types - BExceptions are rare, so simply predicting no exceptions is very accurate
- CThe way in which an object is accessed by a subject
- Dnone
- AExceptions detected at end of instruction execution pipeline, special hardware for various
64Speculating on Exceptions “Recovery mechanism” is -
- AOnly write architectural state at commit point, so can throw away partially executed instructions
after exception - BExceptions are rare, so simply predicting no exceptions is very accurate
- CAn entity capable of accessing objects
- Dnone
- AOnly write architectural state at commit point, so can throw away partially executed instructions
65What is a RT?
- ARename Table
- BRecall Table
- CRelocate Table
- DRemove Table
66What is a FL?
- AFree List
- BFree Last
- CFree Leg
- DFree Launch
67What is an IQ?
- AIssue Queue
- BInternal Queue
- CInterrupt Queue
- DInstruction Queue
68At VLIW “Superscalar Control Logic Scaling” which parameters are used?
- AWidth and Lifetime
- BWidth and Height
- CTime and Cycle
- DLength and Addition
69Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?- ARegister name
- BInstruction cache
- CData tags
- DData cache
Información
- Descripción
- God Philosophy Test sobre CSA Last p1, creado por хомяк убийца el 30/03/2019.
- Autor
- хомяк убийца
- Idioma
- English
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