Test
CSA (115) ⊙ IITU 2017
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Preguntas del test (121)
1Associative Mapping
- A• Each block mapped to any cache location
- B• Each memory block is mapped to exactly one block in the cache
- C• Each block mapped to subset of cache locations
2Direct Mapping
- A• Each block mapped to any cache location
- B• Each memory block is mapped to exactly one block in the cache
- C• Each block mapped to subset of cache locations
3Set-Associative Mapping
- A• Each block mapped to any cache location
- B• Each memory block is mapped to exactly one block in the cache
- C• Each block mapped to subset of cache locations
4• Structural hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
5• Data hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
6• Control hazards
- Adifferent instructions in different stages (or the same stage) conflicting for the same resource
- Ban instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- Cfetch cannot continue because it does not know the outcome of an earlier branch – special case of a data hazard
7• Compulsory misses
- AThe very first access to a block cannot be in the cache
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- COccurs if the block placement strategy is not fully associative
8• Capacity misses
- AThe very first access to a block cannot be in the cache
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- COccurs if the block placement strategy is not fully associative
9• Conflict misses
- AThe very first access to a block cannot be in the cache
- BOccurs if the cache cannot contain all the blocks needed during execution of a program
- COccurs if the block placement strategy is not fully associative
104) Choose the feature(s) of first generation computer architecture
- A• Vacuum tubes, Assembly language
- B• Multilevel Caches
- C• Avoiding Address Translation during Cache Indexing
115) A common measure of performance for a processor is the rate at which instructions are executed, called
- A• CPI
- B• Clock Rate
- C• MFLOPS
- D• MIPS
126) A technique used in advanced microprocessors where the microprocessor begins executing a first instruction before the second has been completed is called pipelining
- AVerdadero
- BFalso
137) Choose the features of third generation computer architecture
- A• Object-Oriented Programming
- B• Graphics
- C• Timesharing
- D• Floating point arithmetic
- E• Use of cache memory
148) Choose advanced cache optimizations
- A• Giving Reads Priority over Writes
- B• Larger Cache Size
- C• Hardware Prefetching of Instructions and Data
- D• Merging Write Buffer
- E• Critical Word First and Early Restart
159) Choose basic cache optimizations
- A• Compiler-Controlled Prefetching
- B• Nonblocking Caches
- C• Small and Simple First-Level Caches
- D• Multilevel Caches
- E• Avoiding Address Translation during Cache Indexing
1610) Choose data dependences
- A• Read-After-Read
- B• Read-After-Write
- C• Write-After-Write
- D• Write-After-Read
1711) Choose hazard for the following definition: an instruction cannot continue because it needs a value that has not yet been generated by an earlier instruction
- A• Data
- B• Structural
- C• Control
1812) Choose hazard for the following definition: different instructions in different stages (or the same stage) conflicting for the same resource
- Ao Structural
- Bo Data
- Co Control
1913) Choose hazard for the following definition: fetch cannot continue because it does not know the outcome of an earlier branch - special case of a data hazard
- Ao Control
- Bo Structural
- Co Data
2014) Choose the access method(s)
- Ao Parallel Access
- Bo Indirect Access
- Co Random Access
- Do Direct Access
- Eo Sequential Access
2115) Choose the component of SSD for the following definition: High speed RAM memory components used for speed matching and to increased data throughput
- Ao Data buffer/cache
- Bo Flash Memory Components
- Co Addressing
- Do Controller
- Eo Error Correction
2216) Choose the component of SSD for the following definition: Individual NAND flash chips
- Ao Flash Memory Components
- Bo Addressing
- Co Data buffer/cache
- Do Controller
- Eo Error Correction
2317) Choose the component of SSD for the following definition: Logic for error detection and correction
- Ao Error Correction
- Bo Addressing
- Co Data buffer/cache
- Do Controller
- Eo Flash memory components
2418) Choose the component of SSD for the following definition: Logic that performs the selection function across the flash memory components
- Ao Addressing
- Bo Flash Memory Components
- Co Data buffer/cache
- Do Controller
- Eo Error Correction
2519) Choose the component of SSD for the following definition: provides SSD device level interfacing and firmware execution
- Ao Controller
- Bo Addressing
- Co Data buffer/cache
- Do Error correction
- Eo Flash memory components
2620) Choose the components of SSD
- Ao Controller
- Bo Addressing
- Co Data buffer/cache
- Do Data size
- Eo Memory hierarchy
2721) Choose the definition for capacity misses
- Ao Occurs if the cache cannot contain all the blocks needed during execution of a program
- Bo The very first access to a block cannot be in the cache
- Co Occurs if the block placement strategy is not fully associative
2822) Choose the definition for compulsory misses
- Ao Occurs if the cache cannot contain all the blocks needed during execution of a program
- Bo Occurs if the block placement strategy is not fully associative
- Co The very first access to a block cannot be in the cache
2923) Choose the definition for conflict misses
- Ao Occurs if the block placement strategy is not fully associative
- Bo Occurs if the cache cannot contain all the blocks needed during execution of a program
- Co The very first access to a block cannot be in the cache
3024) Choose the element(s) of cache design
- Ao Tag
- Bo Latency
- Co AMAT
- Do Mapping Function
- Eo Replacement Algorithm
- Fo Number of Caches
3125) Choose the element(s) of cache design
- Ao Tag
- Bo AMAT
- Co Latency
- Do Cache Size
- Eo Line Size
- Fo Number of Caches
3226) Choose the feature(s) of first generation computer architecture
- Ao Magnetic core memory
- Bo Semiconductor memory
- Co Machine code
- Do Assembly language
- Eo Vacuum tubes
3327) Choose the feature(s) of fourth generation computer architecture
- Ao Object-Oriented programming
- Bo Wide spread use of data communications
- Co Smallest in size
- Do Use of cache memory
- Eo Use of drum memory or magnetic core memory
3428) Choose the feature(s) of second generation computer architecture
- Ao High level languages
- Bo Transistors
- Co 2 Kb memory, 10 KIPS
- Do 2 Mb memory, 5 MIPS
- Eo Different types of supported instructions
3529) Choose the feature(s) of third generation computer architecture
- Ao Object-Oriented programming
- Bo Floating point arithmetic
- Co Timesharing
- Do Use of cache memory
- Eo Graphics
3630) Choose the key characteristics of computer memory systems
- Ao Location
- Bo Unit of Transfer
- Co Access Method
- Do Stalling
- Eo Hazards
3731) Choose the key characteristics of computer memory systems
- Ao Capacity
- Bo Performance
- Co Organization
- Do Instruction Fetch
- Eo Instruction Decode
3832) Choose the key characteristics of computer memory systems
- Ao %20% Physical Type
- Bo %20% Physical Characteristics
- Co %20% Access Method
- Do %20% Unit of Transfer
- Eo %20% Performance
3933) Choose the performance factor
- Ao Cache Size
- Bo Line Size
- Co Instruction Count
- Do Number of Processor Cycles
- Eo Number of memory references
4034) Choose the performance factor(s)
- Ao Cache Size
- Bo Line Size
- Co Instruction Count
- Do Number of Processor Cycles
- Eo Number of memory references
4136) Choose the physical characteristic(s) of disk systems
- Ao Disk system implementstion
- Bo Disk Size
- Co Head Mechanism
- Do Head Motion
- Eo Disk Portability
4236) Choose the physical characteristic(s) of disk systems
- Ao Disk system implementstion
- Bo Disk Size
- Co Head Mechanism
- Do Head Motion
- Eo Disk Portability
4337) Choose the right formula for AMAT
- Ao AMAT \= Hit time + Miss rate + Miss penalty
- Bo AMAT \= Hit time * Miss rate + Miss penalty
- Co AMAT \= Hit time * Miss rate * Miss penalty
- Do AMAT \= Hit time + Miss rate * Miss penalty
4438) Choose the system attribute(s) by which the performance factors are influenced
- Ao Cache size
- Bo Unit of Transfer
- Co Compiler Technology
- Do Processor Implementation
- Eo Cache and memory hierarchy
4539) Choose the type(s) of auxiliary memory
- Ao Flash Memory
- Bo Optical Disk
- Co Hard Drive
- Do SSD
- Eo RAM
4640) Choose the years of the first generation computer architecture
- Ao 1958-1964
- Bo 1964-1974
- Co 1974-present
- Do 1945-1964
- Eo 1945-1958
4741) Choose the years of the second generation computer architecture
- Ao 1945-1958
- Bo 1964-1974
- Co 1974-present
- Do 1945-1964
- Eo 1958-1964
4842) Choose two types of models for a computing machine
- Ao Harvard architecture
- Bo Von Neumann architecture
- Co Oxford architecture
- Do Stanford architecture
4943) CPU Time \= I * CPI / R. Which parameter requires special profiling software?
- Ao Cycles Per instruction
- Bo Execution time
- Co Clock Rate
- Do Numbers of instructions
5044) Floating point performance is expressed as
- Ao CPI
- Bo FLOPS
- Co MIPS
- Do MFLOPS
5145) For random-access memory, the time it takes to perform a read or write operation is called
- Ao Clock Rate
- Bo CPI
- Co Access Time
- Do Latency
52Four bits make octal digit
- AVerdadero
- BFalso
5347) Halting the flow of instructions until the required result is ready to be used is called
- Ao waiting
- Bo delaying
- Co halting
- Do stalling
5448) How a binary digit is called?
- Ao byte
- Bo digit
- Co kilobyte
- Do bit
5549) How a memory unit accessed by contents is called?
- Ao Associative Memory
- Bo Content Addressable Memory
- Co Auxiliary Memory
- Do Cache Memory
- Eo Virtual Memory
5650) How external nonvolatile memory is called?
- Ao Secondary memory
- Bo Main memory
- Co Cache memory
- Do Virtual memory
5751) How many access methods are there?
- A3
- B2
- C4
- D5
- E6
5852) how many elements of cache design are there?
- A2
- B4
- C6
- D7
5953) How many generations of computer architecture are there?
- A4
- B5
- C6
- D7
6054) How many number systems are there?
- A1
- B2
- C3
- D4
6155) How many performance factors are there
- A5
- B6
- C4
- D3
6256) How many physical characteristics of disk systems are there?
- A4
- B5
- C6
- D7
6357) How the stage in which the results of the operation are written to the destination register is called?
- Ao Instruction Fetch
- Bo Write Back
- Co Instruction Decode
- Do Execution
- Eo Memory read/write
6458) IBM System/360 Model 91 was introduced in 1966
- AVerdadero
- BFalso
6559) In 1976 Apple II computer model was released
- AVerdadero
- BFalso
6660) In execution stage identification of the operation is performed
- AVerdadero
- BFalso
6761) In LRU replacement algorithm, the block that is in the cache longest is replaced
- AVerdadero
- BFalso
6862) In virtual memory, memory can be used efficiently because a section of program always loaded
- AVerdadero
- BFalso
6963) In which cache memory mapping technique any block from main memory can be placed anywhere in the cache?
- Ao Associative Mapping
- Bo Set Associative Mapping
- Co Direct Mapping
7064) In which cache memory mapping technique any memory block is mapped to exactly one block in the cache?
- Ao Direct Mapping
- Bo Set Associative Mapping
- Co Associative Mapping
7165) In which cache memory mapping technique any memory block mapped to subset of cache locations?
- Ao Set Associative Mapping
- Bo Direct Mapping
- Co Associative Mapping
7266) Into how many parts a program (or algorithm) which can be parallelized can be split up?
- A2
- B3
- C4
- D5
7367) Select cache optimizations to reduce miss penalty
- Ao Multilevel Caches
- Bo Giving Reads Priority over Writes
- Co Higher associativity
- Do Way Prediction
7468) Select cache optimizations to increase the Cache Bandwidth
- Ao Nonblocking Caches
- Bo Multibanked Caches
- Co Pipelined Cache Access
- Do Small and Simple First-Level Caches
- Eo Multilevel Caches
7569) Octal and hexadecimal numbers are hard on use and conversion
- AVerdadero
- BFalso
7670) Physical address used by program, and which OS must translate into virtual address
- AVerdadero
- BFalso
77Pipelining can only be implemented on hardware
- AVerdadero
- BFalso
78Process of instruction execution is divided into two or more steps, called
- Ao pipelining
- Bo pipe stages
- Co pipe segments
- Do instruction execution
- Eo pipeline hazard
7973) ROM is the place in a computer where the operating system, application programs, and data in current use are kept.
- AVerdadero
- BFalso
8074) Choose the features of first generation computer architecture
- Ao Vacuum tubes
- Bo Assembly language
- Co Magnetic core memory
- Do Semiconductor memory
- Eo Machine code
8175) How a memory unit accessed by contents is called?
- Ao Associative Memory
- Bo Content Addressable Memory
- Co Auxiliary Memory
- Do Cache Memory
- Eo Virtual Memory
8276) Choose the access methods
- Ao Random Access
- Bo Parallel Access
- Co Sequential Access
- Do Indirect Access
- Eo Direct Access
8377) Which type of memory accessed via the input/output channels?
- Ao Auxiliary Memory
- Bo Secondary Memoory
- Co Main Memory
- Do Cache Memory
- Eo Virtual Memory
8478) Which type of memory stores frequently used data?
- Ao Cache Memory
- Bo Auxiliary Memory
- Co Main Memory
- Do Virtual Memory
- Eo Secondary Memory
8579) Stage in which the instruction is fetched from memory and placed in the instruction register called
- Ao Instruction Fetch
- Bo Instruction Decode
- Co Memory read/write
- Do Execution
- Eo Write Back
8680) Which stage is responsible for storing and loading values to and from memory?
- Ao Instruction Fetch
- Bo Instruction Decode
- Co Execution
- Do Memory read/write
- Eo Write Back
8781) How the stage in which the results of the operation are written to the destination register is called?
- Ao Instruction Fetch
- Bo Instruction Decode
- Co Execution
- Do Memory read/write
- Eo Write Back
8882) Select cache optimizations to reduce hit time (both basic and advanced)
- Ao Avoiding Address Translation during Cache Indexing
- Bo Small and Simple First-Level Caches
- Co Way Prediction
- Do Compiler Optimizations
- Eo Compiler-Controlled Prefetching
8983) Select the correct interpretation(s) of Amdahl's Law
- Ao is used to compare computers' performance
- Bo is used calculate the execution time of a program
- Co is used to find the maximum expected improvement
- Do it means that it is the algorithm that decides the speedup not the number of processors
9084) SSD is over 10 times faster than the spinning disks in HDD
- AVerdadero
- BFalso
9185) SSD stands for :
- A• Solid State Drive
- B• Saved State Drive
- C• Solid Slash Drive
- D• Soska State Drive
9286) SSDs are more susceptible to physical shock and vibration
- AVerdadero
- BFalso
9387) SSDs are susceptible to mechanical wear :
- AVerdadero
- BFalso
9488) Static RAM has a reduced power consumption, and a large storage capacity :
- AVerdadero
- BFalso
9589) The "natural" unit of organization of memory is called block :
- AVerdadero
- BFalso
9690) The advantage of virtual memory is that it takes less time to switch between applications because of additional memory :
- AVerdadero
- BFalso
9791) The basic element of a semiconductor memory is the memory cell :
- AVerdadero
- BFalso
9892) The execution time of a program clearly depends on the number of instructions :
- AVerdadero
- BFalso
99he more clock rate of processor, the faster is processor :
- AVerdadero
- BFalso
10094) The particular block is currently being stored is called tag :
- AVerdadero
- BFalso
10195) The RAID scheme consists of 7 levels :
- AVerdadero
- BFalso
10296) The rate at which data can be transferred into or out of a memory unit is called :
- A• Transfer Rate
- B• Speed Rate
- C• Popularity Rate
10397) The time interval is called a clock rate
- AVerdadero
- BFalso
10498) There are three types of cache addresses :
- AVerdadero
- BFalso
10599) There are two types of mapping functions :
- AVerdadero
- BFalso
106100) Three bits make hexadecimal digit :
- AVerdadero
- BFalso
107101) We can find needed block in associatively mapped cache by its block address :
- AVerdadero
- BFalso
108102) What does CPI stand for:
- A• Cycles Per Instruction
- B• Circles Per Instruction
- C• Cycles Per Intersection
- D• Curcuits Per Instruction
109103) What does LRU stand for? :
- A• Least Recently Used
- B• Least Rarely Used
- C• Least Recently Unified
- D• Less Recently Used
110104) What does RAID stand for?:
- A• Redundant Array of Independent Disks
- B• Reduced Array of Independent Disks
- C• Redundant Array of Independent Dots
- D• Restructered Array of Independent Disks
111105) What is included into performance characteristic of computer memory systems? :
- AAccess time
- BCycle Time
- CTransfer Rate
- DSpeed rate
112106) What is included into physical type characteristic of computer memory systems? :
- A• Semiconductor
- B• Magnetic
- C• Laser
- D• Tapes
113107) What is time elapsed to program execution? :
- A• CPU Time + I/O waiting
- B• Other programs
- C• Cycle Time
- D• Access time
114108) Which digits are used in octal number system? :
- A0-7
- B0-8
- C1-8
- D1-7
115109) Which stage is responsible for storing and loading values to and from memory?
- A• Memory read/write
- B• Write back
- C• Memory update
- D• Memory allocation
116110) Which type of memory accessed via the input/output channels :
- A• Auxiliary Memory
- B• Secondary Memory
- C• Virtual memory
- D• Cache memory
117111) Which type of memory stores frequently used data :
- A• Cache Memory
- B• Virtual Memory
- C• Secondary Memory
- D• Axuilary Memory
118112) Word is the "natural" unit of organization of memory :
- AVerdadero
- BFalso
119113) Halting the flow of instructions until the required result is ready to be used is called :
- A• stalling
- B• hailing
- C• falling
- D• feeling
120114) In virtual memory, memory can be used efficiently because a section of program always loaded :
- AVerdadero
- BFalso
121115) Choose the key characteristics of computer memory systems
- APhysical Type
- BPhysical Characteristics
- CAccess Method
- DUnit of Transfer
- EPerformance
- FNone of them
Información
- Descripción
- Test sobre CSA (115) ⊙ IITU 2017, creado por Zhandos Ainabek el 20/12/2017.
- Autor
- Zhandos Ainabek
- Idioma
- English
- Visitas
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- Valoración
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