Test
CMOS Inverter switching characteristics
Este test tiene tipos de pregunta que se abren en el reproductor de siempre.
Preguntas del test (2)
1To define Rise Time and Fall Time of CMOS Inverter. Rise Time is time delay from [blank_start]90%[blank_end] of the output voltage to [blank_start]10%[blank_end] of the output voltage; Fall Time is time delay from [blank_start]10%[blank_end] of the output voltage to [blank_start]90%[blank_end] of the output voltage.
- A90%
- B10%
- C50%
- D10%
- E50%
- F90%
- G10%
- H50%
- I90%
- J90%
- K50%
- L10%
2To define the propagation delay time of CMOS Inverter. Propagation Delay from High to Low is time delay from V(OH) to [blank_start]50%[blank_end] of the output voltage; Propagation Delay from Low to High is time delay from V(OL) to [blank_start]50%[blank_end] of the output voltage.
- A50%
- B90%
- C10%
- D50%
- E10%
- F90%
Información
- Descripción
- CMOS Inverter switching characteristics
- Autor
- shen0109
- Idioma
- English
- Visitas
- 53
- Etiquetas
- Valoración
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