Electrical Engineering Interview Questions


Mainly analog and digital electronics.
Moustafa Hassen
Flashcards by Moustafa Hassen, updated more than 1 year ago
Moustafa Hassen
Created by Moustafa Hassen over 3 years ago

Resource summary

Question Answer
If you put a 0-5 voltstep voltage referenced to ground into the circuits shown, what would you expect the wave forms to look like at the output? Voltage across a capacitor cannot change instantaneously.
The output voltage has 3 distinct regions, Q1 off, Q1 in linear, saturation.
A woofer is for low frequency sounds and a tweeter is for high frequency sounds. A is the woofer and B is the tweeter.
the current through the diode is (12V-0.7V)/ 11.3k Ohms = 1mA. If the diode and transistor are a matched pair, the circuit works as a current mirror and the collector current will be 1mA.
For a BJT, a diode connected transistor is always in the active region. The output will show a slop of about -2mV/degree C
A: -R2/R1 B: 1+ R1/R2
Assume these op-amps have finite gain Ao, what are the closed-loop gains? A: 1/[1/Ao + R1/Ao - R1/R2] B: (R2+R1)/[(R2+R1)/Ao + R2]
Every clock cycle, a charge of C(V1-V2) goes through the capacitor. Current is charge/time. So, average current is C(fc)(V1-V2). Equivalent impedance is found using Ohm's law, = 1/Cfc
Current in R1 is (8-6)/100=20mA. The Zener needs 10mA to sustain the 6V, so the base current is 20mA-10mA = 10mA. Beta =Ie/Ib - 1=100mA/10mA -1 = 9
With a 10:1 turn ratio, the peak Vo is 120 * 1/10=12V. On positive half cycle, diode doesn't conduct so output voltage is 6V. On negative half cycle, diode conducts and output is 12V.
the output voltage would look like an amplified sinusoidal wave with polarity opposite of the input signal. The gain = -gm*RL, gm = Ic/Vt. So, gain = IcRL/Vt. IcRL = 260mV, so gain = -10
Beta(Beta + 1)
Drain current Id=Idss(1-Vgs/Vp)^2. Use the two cases given to get two equations and use them to find Idss and Vp. Idss=9.8mA and Vp=-2.45V
For a passive RC low pass filter, is the output voltage across the resistor or capacitor? Capacitor
Is an RC integrator circuit a low or high pass filter? low pass
In a RC high pass filter, is the output voltage across the resistor or capacitor? Resistor
Is a RC differentiator circuit low or high pass? high pass
Explain a linear voltage regulator Uses a transistor controlled by a differential amplifier to compare the output voltage with a reference voltage and adjusts transistor to maintain the desired constant output
Explain switching voltage regulator. It converts dc input voltage to a pulsed voltage applied to a power transistor. Output is fed back into a circuit that controls the power transistor's on and off times to maintain constant output voltage
In Verilog, write code that swaps contents of 2 registers with and without a temporary register. With temp reg ; always @ (posedge clock) begin temp=b; b=a; a=temp; end Without temp reg; always @ (posedge clock) begin a <= b; b <= a; end
In Verilog, what is the difference between blocking and non-blocking statements? A blocking statement uses = and it evaluates that single statement before moving on the other statements. A non blocking statement uses <= and it evaluates the right hand sides of all the non blocking statements before updating the left hand sides
How does switching frequency impact regulator designs? Higher switching frequency means it can use smaller capacitors and inductors but it also brings more noise in circuit.
In Verilog, how do you open a file for reading and writing? Reading: file = $fopenr("filename"); Writing: file = $fopenw("filename");
What's a common function of a differential amplifier? For a differential pair, it multiplies the voltage difference between 2 inputs by the differential gain
What is a class in C++? A class is a user defined data type, that contains its own properties and functions. Syntax: class student { //data members; //function members; }
For a current mirror, should the output impedance be low or high? What about input impedance? Output impedance should be high and input impedance should be low
In Verilog, what are different ways to close a file? Closing file for input: r = $fcloser(file); Closing file for output: r = $fclosew(file);
What is an object? An object is an instance of a class and can operate on the class's data and functions. Syntax: Student s = new Student();
Show full summary Hide full summary


How to Create A Mindmap
Diffusion and osmosis
Cold War Timeline
GCSE AQA Citizenship Studies: Theme 1
I Turner
The Cold War: An Overview
Andrea Leyden
Camera Angles
English Basic Grammar
Using GoConqr to teach English literature
Sarah Egan
Using GoConqr to study History
Sarah Egan
Flashcards for CPXP exam
Lydia Elliott, Ed.D
1PR101 2.test - Část 15.
Nikola Truong