Processor components/ performance 1.1.1

Question	Answer
Arithmetic & Logic Unit (ALU)	Completes arithmetical & logical operations.
Control unit	Directs operations of the CPU. Controls/ coordinates activities of CPU, manages flow of data, decodes instructions, stores data back in memory.
Registers: Program counter (PC)	Holds address of next instruction to be executed.
Registers: Accumulator (ACC)	Stores results from calculations.
Registers: Memory Address Register	Holds address of location to be read from or written to.
Registers: Memory Data Register (MDR)	Temporarily stores data read or needs to be written.
Registers: Current Instruction Register (CIR)	Holds current instruction being executed in operand & opcode.
What is a bus?	Set of parallel wires that connect two or more components inside CPU.
Data bus	Bi-directional. Used to transport data & instructions between components.
Address Bus	Used to transmit memory address specifying where data is to be sent or retrieved from.
Control Bus	Bi-directional. Used to transmit control signals between internal & external components. Coordinates use of address/ data buses.
What is meant by pipelining?	Process of completing fetch-decode-execute cycles of 3 separate instructions simultaneously. While one instruction is being executed, another can be decoded and another fetched.
What is the Fetch-Decode-Execute cycle?	The fetch-decode-execute cycle is the sequence of operations that are completed in order to execute an instruction.
Describe the process of the Fetch-Decode-Execute cycle. (1)	Address from PC copied to MAR. Instruction held at address copied to MDR by data bus. Contents of PC increased by 1. Value held in the MDR copied to CIR.
Describe the process of the Fetch-Decode-Execute cycle. (2)	Decode: CU decodes contents of CIR to opcode (type of ins/ hardware used to execute it) & operand. Execute phase: decoded instruction is executed.
What is Von-Neumann Architecutre?	Same data bus used to transfer data & instructions. Same Address bus used to transfer addresses of data & instructions. Word size (bits processed) same for all memory.
What is Harvard architecture?	Separate memory for instructions/data. Uses embedded processors. E.g. real-time OS like traffic lights, navigation system. Word size may be larger for instructions due to higher memory use.
Advantages of Von Neumann Architecture:	Cheaper to develop as CU easier to design. Handling just one memory block is simpler and easier to achieve. Less physical space is required than Harvard.
Advantages of Harvard Architecture:	Quicker execution as data/instructions fetched in parallel (dif processors execute multiple calculations at same time). Memories can be different sizes. Used in many systems e.g. embedded systems, mobiles
What is contemporary processing?	Modern combo of Harvard/ Von Neumann architecture. Von Neumann: data/instructions in 1 main memory. Harvard: divide cache into instruction cache and data cache.
Factors affecting CPU performance: Clock speed	Generates signals, switching between 0-1. All processor activities begin on a clock pulse (clock cycle), Clock cycle per sec = 1 hertz. The greater the clock speed, the faster instructions will be executed.
Factors affecting CPU performance: Number of cores	Core = independent processor able to run its own fetch-execute cycle. A comp w/ multiple cores can complete multiple fetch-execute cycle at a time. Dual-core processor, may not perform 2x as fast, software may be unable to take full advantage of both processors.
Factors affecting CPU performance: Amount/ type of Cache memory	Cache memory stores commonly used data so it can be accessed faster. As it fills up, unused instructions are replaced. Level 1-3 cache: very fast- slow memory cell, small-large capacity.

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Processor components/ performance 1.1.1

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	Created by Qashrina Collier about 3 years ago