Flashcards
Processor components/ performance 1.1.1
Cards in this deck (23)
- 1Arithmetic & Logic Unit (ALU)Completes arithmetical & logical operations.
- 2Control unitDirects operations of the CPU.
Controls/ coordinates activities of CPU, manages flow of data, decodes instructions, stores data back in memory. - 3Registers: Program counter (PC)Holds address of next instruction to be executed.
- 4Registers: Accumulator (ACC)Stores results from calculations.
- 5Registers: Memory Address RegisterHolds address of location to be read from or written to.
- 6Registers: Memory Data Register (MDR)Temporarily stores data read or needs to be written.
- 7Registers: Current Instruction Register (CIR)Holds current instruction being executed in operand & opcode.
- 8What is a bus?Set of parallel wires that connect two or more components inside CPU.
- 9Data busBi-directional. Used to transport data & instructions between components.
- 10Address BusUsed to transmit memory address specifying where data is to be sent or retrieved from.
- 11Control BusBi-directional. Used to transmit control signals between internal & external
components. Coordinates use of address/ data buses. - 12What is meant by pipelining?Process of completing fetch-decode-execute cycles of 3 separate instructions simultaneously. While one instruction is being executed, another can be
decoded and another fetched. - 13What is the Fetch-Decode-Execute cycle?The fetch-decode-execute cycle is the sequence of operations that are completed in order to execute an instruction.
- 14Describe the process of the Fetch-Decode-Execute cycle. (1)Address from PC copied to MAR.
Instruction held at address copied to MDR by data bus. Contents of PC increased by 1.
Value held in the MDR copied to CIR. - 15Describe the process of the Fetch-Decode-Execute cycle. (2)Decode: CU decodes contents of CIR to opcode (type of ins/ hardware used to execute it) & operand.
Execute phase: decoded instruction is executed. - 16What is Von-Neumann Architecutre?Same data bus used to transfer data & instructions. Same Address bus used to transfer addresses of data & instructions.
Word size (bits processed) same for all memory. - 17What is Harvard architecture?Separate memory for instructions/data.
Uses embedded processors. E.g. real-time OS like traffic lights, navigation system.
Word size may be larger for instructions due to higher memory use. - 18Advantages of Von Neumann Architecture:Cheaper to develop as CU easier to design.
Handling just one memory block is simpler and easier to achieve.
Less physical space is required than Harvard. - 19Advantages of Harvard Architecture:Quicker execution as data/instructions fetched in parallel (dif processors execute multiple calculations at same time).
Memories can be different sizes.
Used in many systems e.g. embedded systems, mobiles - 20What is contemporary processing?Modern combo of Harvard/ Von Neumann architecture.
Von Neumann: data/instructions in 1 main memory.
Harvard: divide cache into instruction cache and data cache. - 21Factors affecting CPU performance: Clock speedGenerates signals, switching between 0-1. All processor activities begin on a clock pulse (clock cycle),
Clock cycle per sec = 1 hertz.
The greater the clock speed, the faster instructions will be executed. - 22Factors affecting CPU performance: Number of coresCore = independent processor able to run its own fetch-execute cycle. A comp w/ multiple cores can complete multiple fetch-execute cycle at a time.
Dual-core processor, may not perform 2x as fast, software may be unable to take full advantage of both processors. - 23Factors affecting CPU performance: Amount/ type of Cache memoryCache memory stores commonly used data so it can be accessed faster.
As it fills up, unused instructions are replaced.
Level 1-3 cache: very fast- slow memory cell, small-large capacity.
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- A level Computing (Computing Paper 1) Flashcards on Processor components/ performance 1.1.1, created by Qashrina Collier on 29/04/2021.
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