Computer Science 1.1.1

Registers
1. MDR
  1. Stores data that has been fetched from or stored in memory.
2. CIR
  1. Stores the most recent fetched instruction, waiting to be decoded and executed.
3. PC
  1. Contains the location of the instruction being executed at the current time.
4. MAR
  1. Stores the address of the data that are to be fetched from or sent to.
Buses
1. Data
  1. Carries data between the processor and the memory.
2. Address
  1. Carries the address of the memory location being read from or written to.
3. Control
  1. Sends control signals from the control unit.
Fetch-Decode-Execute Cycle
1. Fetch
  1. 1.Address of data is placed on address bus and is fetched from the memory.
  2. 2.Data from this address travels from memory to CPU via data bus.
2. Decode
  1. After data loaded into CIR, it's sent to the CU to decode.
3. Execute
  1. Contents then sent to MDR then to ALU, where an addition is performed. Results are stored in the ACC.
More CPU Processes
1. ALU
  1. Carries out calculations and logical decisions. Results stored in Accumulator.
2. CU
  1. Sends signals to co-ordinate how the CPU works. Decoding happens here.
3. ACC
  1. Stores results of calculations made by ALU.
Architecture
1. Von Neumann
  1. Describes a computer with a single control unit that sequentially works through instructions.
  2. Bottleneck is caused by instructions and data sent along data bus so only one can be performed at once.
2. Harvard
  1. Data and instructions are stored in separate memory units with separate buses for efficiency.
  2. Much more efficient than the Von Neumann architecture due to the separate memory units for data and instructions.

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Computer Science 1.1.1

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	Created by Jamie Fisher over 7 years ago