Quiz
БАЗА 1(Questions 91-185)
Perguntas do quiz (95)
1A branch-prediction cache that stores the predicted address for the next instruction after a branch
- Abranch target buffer
- Bdata buffer
- Coptical buffer
2Buffering the actual target instructions allows us to perform an optimization which called:
- Abranch folding
- Bbranch prediction
- Ctarget instructions
- Dtarget address
3Which is not the function of integrated instructions fetch unit:
- AInstruction memory commit
- BIntegrated branch prediction
- CInstruction prefetch
- DInstruction memory access and buffering
4What is the simple technique that predict whether two stores or a load and a store refer to the same memory address:
- AAddress aliasing prediction
- BBranch prediction
- CIntegrated branch prediction
5What is a topology in interconnection networks?
- AIt indicates how the nodes a network are organised
- BIt is the minimum distance between the farthest nodes in a network
- CNumber of edges connected with a node is called node degree
6What is a network diameter?
- AIt is the minimum distance between the farthest nodes in a network
- BIt indicates how the nodes a network are organised
- CNumber of edges connected with a node is called node degree
7What is a node degree?
- ANumber of edges connected with a node is called node degree
- BIt indicates how the nodes a network are organised
- CIt is the minimum distance between the farthest nodes in a network
8What is a bisection bandwidth?
- ANumber of edges required to be cut to divide a network into two halves is called bisection bandwidth
- BIt indicates how the nodes a network are organised
- CIt is the minimum distance between the farthest nodes in a network
9What is a network throughput?
- AIt indicates how the nodes a network are organised
- BIt is delay in transferring the message between two nodes
- CIt is indicative measure of the message carrying capacity of a network
- DIt is the minimum distance between the farthest nodes in a network
10What is a data routing functions?
- AThe functions which when executed establish the path between the source & destination
- BIt is indicative measure of the message carrying capacity of a network
- CIt is the minimum distance between the farthest nodes in a network
11What is a hardware cost?
- AIt indicates how the nodes a network are organised
- BThe data routing functions are the functions which when executed establish the path between the source and the destination
- CIt refers to the cost involved in the implementation of an interconnection network
- DIt is an indicative measure of the message carrying capacity of a network
12What is a blocking and non-blocking network?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed establish the path between the source and the destination
- Cnetwork In non-blocking networks the route from any free input node to any free output node can always be provided
- DIt is and indicative measure of the message carrying capacity of a network
13Design issue of interconnection network?
- ASoftware Cost
- BHardware Cost
- CRLP
- DSymmetry of the network
14Design issue of interconnection network (нет ответа в базе)
- ADimension and size of network
- BBroadcast and Multicast
- CHardware Cost
- DRLP
15What is the Message Size?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed establish the path between the source and the destination
- CHow much data a processor can send in one time unit
- DIt is and indicative measure of the message carrying capacity of a network
16What is a Data transfer time?
- AIt indicates how the nodes a network are organized
- BThe data routing functions are the functions which when executed establishe the path between the source and the destination
- CHow long does it take for a message to reach to another processor
- DIt is and indicative measure of the message carrying capacity of a network
17Select two-dimensional network (в какой то базе interconnection network)
- AMesh
- BLinear Array
- CCross Bar
18Select multi-dimensional network (в какой то базе interconnection network)
- ALinear Array
- BCross Bar
- CCube
19Select multi-dimensional network (в какой то базе interconnection network)
- ALinear Array
- BCross Bar
- CHyper Cube
20Select non-blocking network (в какой то базе interconnection network)
- ALinear Array
- BCube
- CCross Bar
21A modified version of the tree network (в какой то базе interconnection network)
- AFat tree
- BCube
- CLinear Array
22A interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
- ASystolic Array
- BCube
- CLinear Array
23A _____________ interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
- AHyper cube
- BCube
- CLinear array
24In computer architecture, __________ is the ability of central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system
- AMultithreading
- BComputing
- CArray processing
25In computing, a __________ is a central processing unit(CPU) that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors compared to scalar processors, whose instructions operate in a single data items
- AMultithreading
- BVector processes
- CComputing
- DArray processing
26A _________ is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behaviour of executing instructions in order
- AMultithreading
- BBranch
- CPrediction
- DArray processing
27A __________ is a digital circuit that tries to guess which way a branch (e.g. an if-then-else structure) will go before this is known for sure
- AMultithreading
- BBranch
- CBranch Prediction
28________________ optimization technique where a computer system performs some task that may not be actually needed
- AMultithreading
- BBranch
- CSpeculative execution
29Select two-dimensional network
- AMesh
- BLinear array
- CCross bar
30Single instruction, single data (SISD)
- Aonly one instruction stream is being acted on by the CPU during any one clock cycle
- Ba type of parallel computer
- CCurrently the most common type of parallel computer - most modern supercomputers fall into this category
31In serial computing
- AMultithreading instructions from each part execute simultaneously on different processors
- BInstructions are executed sequentially one after another
- CA problem is broken into discrete parts that can be solved concurrently
32In parallel computing
- AMultithreading instructions from each part execute simultaneously on different processors
- BInstructions are executed sequentially one after another
- CA problem is broken into discrete parts that can be solved concurrently
33Shared memory …
- AFrom a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
- BA logically discrete section of computational work
- CBreaking a task into steps performed by different processor units, with inputs streaming through much like an assembly line
34Massively parallel . . .
- AFrom a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
- BRefers to the hardware that comprises a given parallel system - having many processing elements
- CSolving many similar but independent tasks simultaneously, little to no need for coordination between the tasks
35Embarrassingly parallel . . .
- AFrom a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
- BRefers to the hardware that comprises a given parallel system - having many processing elements
- CSolving many similar but independent tasks simultaneously, little to no need for coordination between the tasks
36Network performance depends of what?
- Aperformance of switches and transmission system
- Bperformance of switches
- Cperformance of transmission system
- Dhas no dependencies
37Which one is not the major flavor of Multiple-issue processors:
- Astatistically superscalar processors
- Bdynamically scheduled superscalar processors
- Cstatically scheduled superscalar processors
- DVLIW (very long instruction word) processors
38A _____________ interconnection network is an extension of cube network
- AHyper Cube
- BCube
- CLinear Array
39Pipelining …
- ABreaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
- BA logically discrete section of computational work
- CFrom a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
40What is Personal mobile device (PMD)?
- AA collection of wireless devices with multimedia user interfaces
- BA collection of computers with wireless network adapters
- CA collection of Clusters/Warehouse-scale computers
41Where the embedded microprocessors are used?
- AIn microwaves, washing machines
- BIn Personal Computers
- CIn mobile phones
42What functions has Instruction Set Architecture (ISA)?
- AServes as the boundary between the software and hardware
- BServes as the bridge between CPU and Memory
- CServes as the bridge between CPU and Cache
43What is the TLP?
- ATime Level Parallelism
- BTechnology Level Parallelism
- CTask Level Parallelism
44By Moore's law, growth rate in transistor count on a chip is doubling?
- Aevery 8 to 12 months
- Bevery 12 to 16 months
- Cevery 18 to 24 months
45How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?
- A3
- B2
- C4
46What is the “Module reliability” in Dependability?
- Aa measure of the continuous service accomplishment from a reference initial instant
- Ba measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
- Ca measure of the interruption
47What is response time?
- Athe time between the start and the completion of an event
- BThe time to get an information
- CThe time spent on execution of a program
48The guiding principle of reporting performance measurements should be?
- Areproducibility
- Bresponsibility
- Ccreativity
49What is Temporal Locality?
- Arecently accessed items are likely to be accessed in the near future
- Bitems whose addresses are near one another tend to be referenced close together in time
- Cthe nearest data stored in secondary memory
50What is Spatial Locality?
- Aitems whose addresses are near one another tend to be refer¬enced close together in time
- Brecently accessed items are likely to be accessed in the near future
- Cthe nearest data stored in secondary memory
51What is Amdahl's law?
- ADefines the speedup that can be gained by using a particular feature
- BDefines time spent on execution of a program
- CDefines data gained in one operation
52The most popular scheme is set associative, where a set is?
- Aa group of blocks
- Ba group of instructions
- Ca group of comparatives
53The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- BIf the cache cannot contain all the blocks needed during execution of a program
- CIf the block placement strategy is not fully associative
54The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
- AIf the cache cannot contain all the blocks needed during execution of a program
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- CIf the block placement strategy is not fully associative
55The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
- AIf the block placement strategy is not fully associative
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache
- CIf the cache cannot contain all the blocks needed during execution of a program
56The “natural” unit of organization of memory
- AWord
- BDocument
- CSeveral Computer
57Main element of cache memory is …
- ALine
- BWord
- CString
58Typical levels of Cache memories …
- A1,2,3 levels
- B1,2,3,4,5 levels
- CCache memories have no levels
59Select internal memory …
- AHard Disk
- BCD-ROM
- CProcessor registers
60Select internal memory
- AHard Disk
- BOptical disk
- CMain memory
61Select internal memory
- ACache
- BMagnetic tape
- COptical disks
62Select external memory?
- AProcessor registers
- BCache
- CMain memory
- DHard disks
63Select external memory
- AOptical Disk
- BCache level 1
- CRegisters of processor
64Select external memory
- AMagnetic tape
- BMain memory
- CAll cache memories
65Physical types of memories:
- ADirect, Random
- BDirect, Access time
- CSemiconductor, Optical
66Physical types of memories:
- ASemiconductor, Magnetic
- BWord, Block
- CDirect, Random
67Physical types of memories:
- AMagneto-optical
- BNumber of words
- CNumber of bytes
68Select correct memory hierarchy:
- ACache – Main Memory – Secondary storages
- BSecondary storages - Cache – Main Memory
- CMain Memory – Cache - Secondary storages
69Select correct memory hierarchy:
- AProcessor registers – Cache memory – Main memory
- BCache memory – Main memory - Processor registers
- CCache memory – Processor registers - Main memory
70External, nonvolatile memory is also referred to as …
- Aauxiliary memory
- BMain memory
- CLevels of cache
71Types of cache addresses
- ALogical, Physical
- BDirect, Associative
- CSet Associative
72A logical cache stores data using …
- Avirtual addresses
- Bvirtual addresses and physical addresses
- CPhysical addresses
73The two basic forms of semiconductor random access memory are
- Adynamic RAM (DRAM) and static RAM (SRAM)
- Bmagnetic and optical
- CWinchester and optical disks
74Main element of cache memory
- ATag
- BWord
- CString
75A number of chips can be grouped together to form …
- Aa memory bank
- Ba memory tags
- Ca memory linis
76Data are recorded on and later retrieved from the disk via a conducting coil named
- AThe arm
- BThe slid
- CThe head
77The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
- Amultiple zoned recording
- Bintersector gap
- Cthe constant angular velocity
78To increase density, modern hard disk systems use a technique known as
- Amultiple zone recording
- Bthe constant angular velocity
79… can be removed and replaced with another disk.
- AProcessor registers
- BA nonremovable disk
- CA removable disk
80For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
- Adouble sided
- Bsingle sided
- Cno sides
81The set of all the tracks in the same relative position on the platter is referred to as …
- Aa cylinder
- Ba square
- Ca circle
82On a movable head system, the time it takes to position the head at the track is known as …
- Atransfer time
- Baccess time
- Cseek time
83The operating system …
- Ais the software that controls the execution of programs on a processor and that manages the processor’s resources.
- Bis one which is understandable by us humans
- Cis a collection of Clusters/Warehouse-scale computers
- Da program that directly executes instructions written in a programming language
84The most important functions of the Operating System are
- AThe scheduling of processes, or tasks
- BCompile C++ program codes
- CInterpret PHP program codes
- DProvide drivers for the remote devices
85The important function of the Operating System is
- AMemory management
- BProvide compiler for high level programming languages
- CIncrease size of cache
86How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
- AProgram execution
- BAccess to I/O devices
- CProgram creation
87How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
- AProgram creation
- BAccess to I/O devices
- CProgram execution
88How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
- AAccess to I/O devices
- BProgram execution
- CProgram creation
89How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
- AControlled access to files
- BAccess to I/O devices
- CSystem access
90How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
- AError detection and response
- BSystem access
- CControlled access to files
91How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
- AAccounting
- BSystem access
- CControlled access to files
92Select two independent dimensions of the Operating System
- Abatch and interactive
- Bbatch and computer operator
- CInteractive and computer operator
93Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
- AAccess Permission (AP), Access Permission Extension (APX)
- BBufferable (B) bit
- CCacheable (C) bit
94Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
- ABufferable (B) bit
- BCacheable (C) bit
- CType Extension (TEX)
95What is a latency?
- AIt indicates how the nodes a network are organized
- BIt is the delay in transferring the message between two nodes
- CIt is the minimum distance between the farthest nodes in a network
Informações
- Descrição
- PC Architecture Quiz sobre БАЗА 1(Questions 91-185), criado por Csse 1502 em 23-05-2018.
- Autor
- Csse 1502
- Idioma
- English
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