Copiar e Editar

CSA IITU Part 1 (235)

Descrição

Quiz sobre CSA IITU Part 1 (235), criado por Hello World em 20-12-2017.
Hello World
Quiz por Hello World, atualizado more than 1 year ago
Hello World
Criado por Hello World mais de 6 anos atrás
1734
22
0

Resumo de Recurso

Questão 1

Questão
130. How many bytes equals Petabyte (PB)?
Responda
  • · Quadrillion
  • · Million
  • · Trillion
  • · Billion
  • · 1000

Questão 2

Questão
129. Which one of the following is a memory whose duty is to store most frequently used data?
Responda
  • · Main memory
  • · Cache
  • · ROM
  • · Auxiliary memory
  • · PROM

Questão 3

Questão
128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
Responda
  • · Binary Adder
  • · Full Adder
  • · Half Adder
  • · Adder
  • · OR gate

Questão 4

Questão
127. The key technology used in IV generation computers is ___.
Responda
  • · MSI
  • · SSI
  • · LSI & VLSI
  • · Transistors
  • · Vacuum Tubes

Questão 5

Questão
126. The computer architecture having stored program is ___.
Responda
  • · Harvard
  • · Von Neumann
  • · Pascal
  • · Ada
  • · Cobol

Questão 6

Questão
125. Stack is a ___list.
Responda
  • · FIFO
  • · LIFO
  • · FILO
  • · OFLI

Questão 7

Questão
124. CACHE memory is implemented using ___.
Responda
  • · Dynamic RAM
  • · Static RAM
  • · EA RAM
  • · ED RAM
  • · EP RAM

Questão 8

Questão
123. What does D stand for in a D flip-flop?
Responda
  • · Direct
  • · Don’t care
  • · Data
  • · Device
  • · Disk

Questão 9

Questão
104. What is a Capacity?
Responda
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · first-reference to a block, occur even with infinite cache
  • · misses that occur because of collisions due to less than full associativity

Questão 10

Questão
103. What is a Compulsory?
Responda
  • · first-reference to a block, occur even with infinite cache
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · misses that occur because of collisions due to less than full associativity

Questão 11

Questão
39. 74. How many elements of the Instruction Set Architecture (ISA)
Responda
  • 8
  • 7
  • 6

Questão 12

Questão
38. 73. What is the MISD one of the categories of computers?
Responda
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Set Data Stream

Questão 13

Questão
36. 72. What is the Instruction Level Parallelism
Responda
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Questão 14

Questão
35. 71. What is the Request Level Parallelism
Responda
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Questão 15

Questão
34. 70. What is the Thread Level Parallelism
Responda
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Questão 16

Questão
33. 69. What is the Vector Architectures and Graphic Processor Units (GPUs)
Responda
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Questão 17

Questão
32. 68. The Application of Brokerage operations how many cost of downtime per hour?
Responda
  • 8.870.000$
  • 7.550.000$
  • 6.450.000$

Questão 18

Questão
31. 67. What is the PMD in computer classes?
Responda
  • Percentage map device
  • Personal mobile device
  • Peak maze development
  • Powerful markup distance

Questão 19

Questão
30. 66. Which distance of price has Clusters/warehouse-scale computers?
Responda
  • 100 – 100.000$
  • 100.000 – 200.000.000$
  • 5.000 – 10.000.000$

Questão 20

Questão
29. 65. How many classes of computers classified?
Responda
  • 7
  • 3
  • 5

Questão 21

Questão
28. 64. What is the RLP?
Responda
  • Request Level Parallelism
  • Research Level Parallelism
  • Random Level Parallelism

Questão 22

Questão
27. 63. How much in percentage single-processor performance improvement has dropped to less than?
Responda
  • 22%
  • 33%
  • 11%

Questão 23

Questão
26. 62. When single-processor performance improvement has dropped?
Responda
  • 2003
  • 2002
  • 2004

Questão 24

Questão
25. 61. What is a RISC computers?
Responda
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer
  • Reduced Instruction Set Computer

Questão 25

Questão
24. 56. Choose the right formula of AMAT(в базе был неверный ответ можете попробовать подать апелляцию)
Responda
  • Average Memory Access time = Hit Time + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Time + Miss time * Miss penalty
  • Average Memory Access time = Hit Rate + Miss time * Miss penalty

Questão 26

Questão
23. What is the total number of writes that hit in the cache?
Responda
  • 588
  • 784
  • 12.5%
  • 0.25%

Questão 27

Questão
22. 30. Definition of Block address:
Responda
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • time to access upper level
  • memory closer to processor

Questão 28

Questão
20. 28. Definition of Block:
Responda
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • memory closer to processor
  • time to access upper level

Questão 29

Questão
19. 27. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
Responda
  • SRAM
  • DRAM
  • RAM

Questão 30

Questão
18. 26. Performance of a machine is determined by:
Responda
  • Instruction count, Clock cycle time, Correlating predictors
  • Instruction count, Clock cycle time, Clock cycle per instruction
  • Clock cycle time, Correlating predictors, Aggressive instruction
  • Clock cycle time, Clock cycles per instruction, Correlating Predictors

Questão 31

Questão
17. 25. Pipe-lining is a unique feature of ___.
Responda
  • CISC
  • IANA
  • ISA
  • RISC

Questão 32

Questão
16. 24. The iconic feature of the RISC machine among the following are
Responda
  • Increased memory size
  • Reduced number of addressing modes
  • Having a branch delay slot
  • All of the above

Questão 33

Questão
15. 23. The Sun micro systems processors usually follow ___ architecture.
Responda
  • CISC
  • ISA
  • ULTRA SPARC
  • RISC

Questão 34

Questão
14. 22. Of the following, identify the memory usually written by the manufacturer.
Responda
  • RAM
  • DRAM
  • SRAM
  • ROM
  • Cache Memory

Questão 35

Questão
13. 21. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
Responda
  • Hit rate
  • Miss rate
  • Access rate
  • Success rate

Questão 36

Questão
12. 20. How many instructions can be implemented in MIPS?
Responda
  • 2 clock cycles
  • 3 clock cycles
  • 4 clock cycles
  • 5 clock cycles

Questão 37

Questão
19. The secondary effect that results from instruction scheduling in large code segments is called ___?
Responda
  • Aggressive instruction
  • Correlating predictors
  • Register predictors
  • Register pressure

Questão 38

Questão
10. 18. The CISC stands for?
Responda
  • Computer Instruction Set Compliment
  • Complete Instruction Set Compliment
  • Computer Indexed Set Components
  • Complex Instruction Set Computer

Questão 39

Questão
9. Assembly line operation is also called as?
Responda
  • Pipelining process
  • Superscalar operation
  • None of the mentioned
  • Von Neumann cycle

Questão 40

Questão
8. 16. Can you solve the Dining Philosophers’ Problem using monitors?
Responda
  • Yes
  • No
  • Yes, but only if there are less than five philosophers
  • No, unless there are more than five philosophers

Questão 41

Questão
7. 15. The central themes of operating system design are all concerned with the management of processes and threads?
Responda
  • Multiprogramming, multiprocessing, distributed processing
  • Multitasking, multiprogramming, multithreading
  • Multiprocessing, uniprocessing, multitasking
  • Multithreading, distributed processing, uniprocessing

Questão 42

Questão
6. 14. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Responda
  • Availability, confidentiality, data integrity, authenticity
  • Safety, accountability, reliability, density
  • Usability, integrity, confidentiality, reliability
  • Flexibility, availability, accountability, authenticity

Questão 43

Questão
5. 13. Which of the following principles has Deadlock?
Responda
  • Execution, Association, Starvation
  • Prevention, Avoidance, Detection
  • Starvation, Detection, Exclusion
  • Exclusion, Avoidance, Starvation

Questão 44

Questão
4. 12. How many principles has Deadlock?
Responda
  • 3
  • 5
  • 2
  • 6

Questão 45

Questão
3. 11. Three techniques are possible for I/O operations:
Responda
  • Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
  • Machine I/O, Architecture I/O, Hardware I/O
  • Object-oriented I/O, Design I/O, Usable I/O
  • Control I/O, Status I/O, Transfer I/O

Questão 46

Questão
2. 10. Cache Design has these properties?
Responda
  • Size, search function, write function, read policy, vector algorithm
  • Size, mapping algorithm, vector function, write policy, replacement function
  • Size, blocking algorithm, search function, replacement vector, read policy
  • Size, block size, mapping function, replacement algorithm, write policy

Questão 47

Questão
1. In Memory Hierarchy, at the Inboard storage which of the following are included:
Responda
  • Magnetic disk
  • Magnetic tape
  • Optical disk
  • Main memory

Questão 48

Questão
180. In Memory Hierarchy, at the Off-line storage which of the following are included:
Responda
  • • Cache
  • • Magnetic disk
  • • Magnetic tape
  • • Main memory

Questão 49

Questão
179. In Memory Hierarchy, at the Outboard storage which of the following are included:
Responda
  • • Cache
  • • Main memory
  • • Magnetic tape
  • • Magnetic disk

Questão 50

Questão
178. How many parts of Memory Hierarchy?
Responda
  • • 5
  • • 4
  • • 2
  • • 3

Questão 51

Questão
177. Which one is concerning to fallacy?
Responda
  • o Predicting cache performance of one program from another
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs

Questão 52

Questão
176. Which one is NOT concerning to pitfall?
Responda
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs
  • o Predicting cache performance of one program from another

Questão 53

Questão
175. ChoosetheEleventhOptimization
Responda
  • o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • o None of them

Questão 54

Questão
174. ChoosetheEightOptimization
Responda
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Critical word first
  • o Nonblocking Caches to Increase Cache Bandwidth
  • o Trace Caches to Reduce Hit Time

Questão 55

Questão
173. Choose the strategy of Seventh Optimization.
Responda
  • o Critical restart
  • o Critical word first
  • o Sequential inter leaving
  • o Merging Write Buffer to Reduce Miss Penalty

Questão 56

Questão
172. Choose the benefit of Cache Optimization.
Responda
  • o Larger block size to reduce miss rate
  • o Bigger caches to increase miss rat
  • o Single level caches to reduce miss penalty
  • o None of them

Questão 57

Questão
171. What is conflict in Cs model?
Responda
  • o If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o None of them

Questão 58

Questão
170. What is capacityin Cs model?
Responda
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them

Questão 59

Questão
169. What is the compulsory in Cs model?
Responda
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Questão 60

Questão
168. How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Responda
  • o the number of prediction entries selected by the branch = 1K.
  • o the number of prediction entries selected by the branch = 2K.
  • o the number of prediction entries selected by the branch = 8K.
  • o the number of prediction entries selected by the branch = 4K.

Questão 61

Questão
167. Branch predictors that use the behavior of other branches to make a prediction are called
Responda
  • o correlating predictors or two-level predictors
  • o branch-prediction buffer
  • o branch table
  • o three level loop

Questão 62

Questão
166. The simplest dynamic branch-prediction scheme is a
Responda
  • o branch-prediction buffer
  • o branch buffer
  • o All answers correct
  • o registrationo registration

Questão 63

Questão
165. Effect that results from instruction scheduling in large code segments is called…?
Responda
  • o register pressure
  • o loop unrolling
  • o loop-level
  • o registration

Questão 64

Questão
164. A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Responda
  • o loop unrolling
  • o RAR
  • o loop-level
  • o loop rolling

Questão 65

Questão
163. What is given is not a hazard?
Responda
  • o RAR
  • o WAR
  • o WAW
  • o LOL

Questão 66

Questão
162. What is RAW (read after write)?
Responda
  • o when j tries to read a source before i writes it, so j incorrectly gets the old value
  • o when j tries to write a source before i writes it
  • o when i tries to read a source before j writes it, so j correctly gets the old value
  • o when a tries to write a source before b read it, so a incorrectly gets the old value

Questão 67

Questão
161. When occurs an output dependence?
Responda
  • o When i and instruction j write the same register or memory location
  • o when i and instruction j write the same adress or memory location
  • o when i and instruction j write the same name
  • o All answers is correct

Questão 68

Questão
160. What is Name dependence?
Responda
  • o name dependence occurs when two instructions use the same register or memory location
  • o name dependence occurs when five or more instructions use the same register or memory location
  • o name dependence occurs when instructions use the same name
  • o All answers is correct

Questão 69

Questão
159. In parallelism have three different types of dependences, tagging him:
Responda
  • o data dependences , name dependences , and surname dependences
  • o datagram dependences , name dependences , and animal dependences
  • o no correct answers
  • o data dependences , name dependences , and control dependences

Questão 70

Questão
158. The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Responda
  • o loop-level parallelism
  • o exploit-level parallelism
  • o high-level minimalism
  • o low-level minimalism

Questão 71

Questão
157. The simplest and most common way to increase the ILP is …?
Responda
  • o to exploit parallelism among iterations of a loop
  • o to exploit minimalism among iterations of a loop
  • o to destroy iterations of a loop
  • o to decrease the minimalism of risk

Questão 72

Questão
156. What is the Pipeline CP = ?
Responda
  • o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • o deal pipeline CPU + Data hazard stalls + Control stalls
  • o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
  • o Structural stalls + Data hazard stalls + Control stalls

Questão 73

Questão
155. The ideal pipeline CPI is a measure of …
Responda
  • o the maximum performance attainable by the implementation
  • o the maximum performance attainable by the instruction
  • o the minimum performance attainable by the implementation
  • o the minimum performance attainable by the instruction

Questão 74

Questão
154. How to decrypt RISC?
Responda
  • o Reduced Instruction Set Computer
  • o Recall Instruction Sell Communication
  • o Rename Instruction Sequence Corporation
  • o Red Instruction Small Computer

Questão 75

Questão
153. What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Responda
  • o Address aliasing prediction
  • o Branch prediction
  • o Integrated branch prediction
  • o Dynamic branch prediction

Questão 76

Questão
152. Which is not the function of integrated instruction fetch unit:
Responda
  • o Instruction memory commit
  • o Integrated branch prediction
  • o Instruction memory access and buffering
  • o Instruction prefetch

Questão 77

Questão
151. Buffering the actual target instructions allows us to perform an optimization which called:
Responda
  • o branch folding
  • o Branch prediction
  • o Target instructions
  • o Target address

Questão 78

Questão
150. A branch-prediction cache that stores the predicted address for the next instruction after a branch
Responda
  • o branch-target buffer
  • o data buffer
  • o frame buffer
  • o optical buffer

Questão 79

Questão
149. Examples of VLIW/LIW:
Responda
  • o TI C6x
  • o MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5

Questão 80

Questão
148. Examples of superscalar(dynamic) :
Responda
  • o None at the present
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o MIPS and ARM
  • o TI C6x

Questão 81

Questão
147. Examples of superscalar(static):
Responda
  • • MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Questão 82

Questão
146. Examples of EPIC:
Responda
  • o Itanium
  • o MIPS and ARM
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Questão 83

Questão
145. Which Multiple-issue processors has not the hardware hazard detection:
Responda
  • o EPIC
  • o Superscalar(dynamic)
  • o Superscalar(static)
  • o Superscalar(speculative)

Questão 84

Questão
144. Which one is not the major flavor of Multiple-issue processors:
Responda
  • o statistically superscalar processors
  • o dynamically scheduled superscalar processors
  • o statically scheduled superscalar processors
  • o VLIW (very long instruction word) processors

Questão 85

Questão
143. Choose the steps of instruction execution:
Responda
  • o issue, execute, write result, commit
  • o execution, commit, rollback
  • o issue, execute, override, exit
  • o begin, write, interrupt, commit

Questão 86

Questão
142. Choose correct fields of entry in the ROB:
Responda
  • o the instruction type, the destination field, the value field, and the ready field
  • o the source type, the destination field, the value field, and the ready field
  • o the program type, the ready field, the parameter field, the destination field
  • o the instruction type, the destination field, and the ready field

Questão 87

Questão
141. How many fields contains the entry in the ROB:
Responda
  • 4
  • 6
  • 5
  • 3

Questão 88

Questão
140. For what the reorder buffer is used :
Responda
  • o To pass parameters through instructions that may be speculated
  • o To pass results among instructions that may be speculated.
  • o To get additional registers in the same way as the reservation stations
  • o To control registers

Questão 89

Questão
139. How this process called: “Operations execute as soon as their operands are available”
Responda
  • o data flow execution
  • o data control execution
  • o instruction execution
  • o instruction field execution

Questão 90

Questão
138. Which of these is NOT characteristics of recent highperformance microprocessors?
Responda
  • o Color
  • o Functional unit capability
  • o Clock rate
  • o Power

Questão 91

Questão
• Popular data structure for organizing a large collection of data items so that one can quickly
Responda
  • o Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • o Popular tables for organizing a large collection of data structure
  • o Popular data structure for updating large collections, so that one can hardly answer questions
  • o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Questão 92

Questão
136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Responda
  • o Achievable ILP with software resource constraints
  • o Limited ILP due to software dependences
  • o Achievable ILP with hardware resource constraints
  • o Variability of ILP due to software and hardware interaction

Questão 93

Questão
135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Responda
  • o Dynamic power
  • o Processing rate
  • o Static power
  • o Processor state

Questão 94

Questão
134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Responda
  • o Static power
  • o Dynamic power
  • o Processing rate
  • o Processor state

Questão 95

Questão
133. If we want to sustain four instructions per clock
Responda
  • o We must fetch more, issue more, and initiate execution on more than four instructions
  • o We must fetch less, issue more, and initiate execution on more than two instructions
  • o We must fetch more, issue more, and initiate execution on less than five instructions
  • o We must fetch more, issue less, and initiate execution on more than three instructions

Questão 96

Questão
132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
Responda
  • o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
  • o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
  • o The number of transistors switching will be proportional to the sustained rate
  • o The performance is proportional to the peak issue rate

Questão 97

Questão
131. Which of the written below is NOT increase power consumption?
Responda
  • o Increasing multithreading
  • o Increasing performance
  • o Increasing multiple cores
  • o Increasing multithreading(повторяется хз что тут )

Questão 98

Questão
130. Which of the following descriptions corresponds to dynamic power?
Responda
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Certainly a design concern
  • o None of the above

Questão 99

Questão
129. Which of the following descriptions corresponds to static power?
Responda
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Proportional to the product of the number of switching transistors and the switching rate Probability
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o All of the above

Questão 100

Questão
128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Responda
  • o Speedup
  • o Efficiency
  • o Probability
  • o Ration

Questão 101

Questão
127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Responda
  • • 90% 10%
  • o 70% 30%
  • o 50% 50%
  • o 89% 11%

Questão 102

Questão
126. What MTTF means:
Responda
  • o mean time to failure
  • o mean time to feauture
  • o mean this to failure
  • o my transfers to failure

Questão 103

Questão
125. Desktop benchmarks divide into __ broad classes:
Responda
  • o two
  • o three
  • o four
  • o five

Questão 104

Questão
124. Systems alternate between two states of service with respect to an SLA:
Responda
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Questão 105

Questão
123. The most companies spend only ____________ of their income on R&D, which includes all engineering.
Responda
  • o 30% to 48%
  • o 4% to 12%
  • o 15% to 30%
  • o 1% to 17%

Questão 106

Questão
122. Volume is a ________ key factor in determining cost.
Responda
  • o second
  • o first
  • o fifth
  • o third

Questão 107

Questão
121. Manufacturing costs that decrease over time are ____
Responda
  • o the learning curve
  • o the cycled line
  • o the regular option
  • o the final loop

Questão 108

Questão
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
Responda
  • o dynamic power
  • o physical energy
  • o constant supply
  • o simple battery

Questão 109

Questão
119. Integrated circuit processes are charecterized by the
Responda
  • o feature size
  • o permanent size n
  • o compex size
  • o fixed size

Questão 110

Questão
118. Products that are sold by multiple vendors in large volumes and are essentialy identical
Responda
  • o boxes
  • o files
  • o folders
  • o commodities

Questão 111

Questão
117. Learning curve itself is best measured by change in...
Responda
  • o bytes
  • o bits
  • o seconds
  • o yeld

Questão 112

Questão
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Responda
  • o bandwidth
  • o throughput
  • o latency
  • o performance

Questão 113

Questão
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Responda
  • o bandwidth
  • o latency
  • o throughput
  • o performance

Questão 114

Questão
1. Network performance depends of what?
Responda
  • o performance of swithes and transmission system
  • o performance of switches
  • o has no dependensies
  • o performance of transmission system

Questão 115

Questão
113. What is a “Kernel” in Cache Memory?
Responda
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables
  • o Execution in user code

Questão 116

Questão
112. What is a “Synchronization” in Cache Memory?
Responda
  • o Execution in user code
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables

Questão 117

Questão
111. What is a “Kernel” in Cache Memory?
Responda
  • o Execution or waiting for synchronization variables
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code

Questão 118

Questão
110. What is a “Synchronization” in Cache Memory?
Responda
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code
  • o Execution or waiting for synchronization variables

Quer criar seus próprios Quizzes gratuitos com a GoConqr? Saiba mais.

Semelhante

Porcentagens e Frações
luciahelenaferre
Matérias para Estudar para o Vestibular
Alice Sousa
Estilos de redação para concursos
Alessandra S.
Exame Nacional de Português 2
Sandra Franco
TEORIA SEXUAL FREUD
eleuterapara
Direito ambiental
GoConqr suporte .
Liderança
Liliane Tubino
CF - Direitos Políticos (positivos e negativos)
Thay Viegas
TGA - Teoria Clássica
Natanael Lima
Redação Oficial
Lavs Agah
ANATOMOFISIOLOGIA - SISTEMA NERVOSO CENTRAL
Keyla Lima
Explore a Biblioteca