PCA_Final [arc2-1, Part-1]

Question

Storage Systems, “Higher associativity to reduce miss rate”

Answer 1

The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

Answer 2

The obvious way to reduce capacity misses is to increase cache capacity

Answer 3

Obviously, increasing associativity reduces conflict misses

Answer 4

The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

Answer 5

The obvious way to reduce capacity misses is to increase cache capacity

Answer 6

Obviously, increasing associativity reduces conflict misses

Answer 7

Wait until no data hazards, then reads the operand

Answer 8

Decode instructions, check for structural hazards

Answer 9

The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size

Answer 10

The obvious way to reduce capacity misses is to increase cache capacity

Answer 11

Obviously, increasing associativity reduces conflict misses

Answer 12

Loads data only into the cache and not the register

Answer 13

Will load the value into register

Answer 14

Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Answer 15

Faults in software (usually) and hardware design (occasionally)

Answer 16

Mistakes by operations and maintenance personnel

Answer 17

Execution or waiting for synchronization variables

Answer 18

Execution in user code

Answer 19

Execution in the OS that is neither idle nor in synchronization access

Answer 20

Average time per task in the queue

Answer 21

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

Answer 22

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Answer 23

Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards

Answer 24

Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards

Answer 25

Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards

Answer 26

Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards

Answer 27

Wait until no control hazards, then reads the operand

Answer 28

Wait until no structural hazards, then reads the operand

Answer 29

Wait until no data hazards, then reads the operand

Answer 30

All memory accesses take one clock cycle

Answer 31

All conditional branches are predicted exactly

Answer 32

All memory addresses are known exactly

Answer 33

Very Long Instruction Word

Answer 34

Very Less Interpreter Word

Answer 35

Very Light Internal Word

Answer 36

Very Low Invalid Word

Answer 37

Software Pipelined

Answer 38

Loop Unrolled

Answer 39

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

Answer 40

Average time per task in the queue

Answer 41

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Answer 42

Miss Address File

Answer 43

Map Address File

Answer 44

Memory Address File

Answer 45

Fetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution

Answer 46

Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Answer 47

Control, exploit, system

Answer 48

Masquerader, misfeasor, clandestine user

Answer 49

Individual, legitimate, authorized

Answer 50

Outside, inside, offside

Answer 51

The obvious way to reduce capacity misses is to increase cache capacity

Answer 52

Obviously, increasing associativity reduces conflict misses

Answer 53

Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Answer 54

Faults in software (usually) and hardware design (occasionally)

Answer 55

Mistakes by operations and maintenance personnel

Answer 56

Architectural Register File

Answer 57

Architecture Relocation File

Answer 58

Architecture Reload File

Answer 59

Architectural Read File

Answer 60

first-reference to a block, occur even with infinite cache

Answer 61

misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Answer 62

cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Answer 63

CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time

Answer 64

CPU time-Cache Miss-Miss Penalty-CPU time

Answer 65

CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Answer 66

Width and Lifetime

Answer 67

Width and Height

Answer 68

Time and Cycle

Answer 69

Length and Addition

Answer 70

Execution in the OS that is neither idle nor in synchronization access

Answer 71

Execution in user code

Answer 72

Execution or waiting for synchronization variables

Answer 73

CPU time-Cache Miss-Miss Penalty-CPU time

Answer 74

CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Answer 75

CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Answer 76

Electronically Erasable Programmable Read-Only Memory

Answer 77

Electronically Extensible Programmable Re-Order Memory

Answer 78

Electronically Executable Programmable Reduce Memory

Answer 79

The time between when a read is requested and when the desired word arrives

Answer 80

The minimum time between unrelated requests to memory

Answer 81

misses in cache / accesses to cache

Answer 82

misses in cache / CPU memory accesses

Answer 83

misses in cache / number of instructions

Answer 84

Also called mirroring or shadowing, there are two copies of every piece of data

Answer 85

It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array

Answer 86

This organization was inspired by applying memory-style error correcting codes to disks

Answer 87

This hazard corresponds to an output dependence

Answer 88

This hazard is the most common type and corresponds to a true data dependence

Answer 89

This hazard arises n antidependence (or name dependence)

Answer 90

Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed

Answer 91

Many applications are dominated by small accesses

Answer 92

Also called mirroring or shadowing, there are two copies of every piece of data

Answer 93

Critical word first and merging write buffer

Answer 94

Pipelined caches, multibanked caches and non-blocking caches

Answer 95

Small and simple first-level caches and way-prediction

Answer 96

This organization was inspired by applying memory-style error correcting codes to disks

Answer 97

It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array

Answer 98

Also called mirroring or shadowing, there are two copies of every piece of data

Answer 99

Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Answer 100

Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

Answer 101

Fetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution

Answer 102

Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block

Answer 103

Hardware prefetching and compiler prefetching

Answer 104

Compiler optimization

Answer 105

Pipelined caches, multibanked caches and non-blocking caches

Answer 106

Rename Table

Answer 107

Recall Table

Answer 108

Relocate Table

Answer 109

Remove Table

Answer 110

Percentage map device

Answer 111

Personal mobile device

Answer 112

Powerful markup distance

Answer 113

Peak maze development

Answer 114

Data dependence

Answer 115

Name dependence

Answer 116

Control dependence

Answer 117

Cache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)

Answer 118

Misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Answer 119

First-reference to a block, occurs even with infinite cache

Answer 120

All conditional branches are predicted exactly

Answer 121

All memory accesses take one clock cycle

Answer 122

All memory addresses are known exactly

Answer 123

Exceptions are rare, so simply predicting no exceptions is very accurate

Answer 124

Only write architectural state at commit point, so can throw away partially executed instructions after exception

Answer 125

None of them

Answer 126

An entity capable of accessing objects

Answer 127

What is the reducing the miss rate?

Answer 128

Performance optimization

Answer 129

Compiler optimization

Answer 130

Time optimization

Answer 131

Double data rate

Answer 132

Density data rate

Answer 133

Dynamic data rate

Answer 134

Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

Answer 135

Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Answer 136

100-100 000$

Answer 137

100 000-200 000 000$

Answer 138

5 000 -10 000 000$

Answer 139

Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Answer 140

Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts

Answer 141

Average time per task in the queue

Answer 142

Multiple instructions streams, set data stream

Answer 143

Multiple instructions streams, single data stream

Answer 144

Multiple instruction stream, multiple data streams

Answer 145

Many applications are dominated by small accesses

Answer 146

Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed

Answer 147

Also called mirroring or shadowing, there are two copies of every piece of data

Answer 148

Will load the value into a register

Answer 149

Loads data only into the cache and not the register

Answer 150

Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.

Answer 151

Exploits parallelism among largely decoupled tasks specified by the programmer or the operating system

Answer 152

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Answer 153

CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Answer 154

CPU time-Cache Miss-Miss Penalty-CPU time

Answer 155

CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Answer 156

Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Answer 157

Faults in software (usually) and hardware design (occasionally)

Answer 158

Mistakes by operations and maintenance personnel

Answer 159

This hazard correspond to an output dependence

Answer 160

This hazard arises from an antidependence (or name dependence)

Answer 161

Scale level approach

Answer 162

Service level agreements

Answer 163

Standard level achievement

Answer 164

Loop unrolled

Answer 165

Software Pipelined

Answer 166

Exploit by remembering the contents of recently accessed locations

Answer 167

Exploit by fetching blocks of data around recently accessed locations

Answer 168

Issue Queue

Answer 169

Internal Queue

Answer 170

Interrupt Queue

Answer 171

Instruction Queue

Answer 172

The time between when the user enters the command and the complete response is displayed

Answer 173

The time for the user to enter the command

Answer 174

The time from the reception of the response until the user begins to enter the next command

Answer 175

Reduced instruction set computer

Answer 176

Research interconnect several computer

Answer 177

Rational interruptible security computer

Answer 178

Operand code

Answer 179

Optional code

Answer 180

Operation code

Answer 181

This hazard arises from an antidependence (or name dependence)

Answer 182

This hazard corresponds to an output dependence

Answer 183

This hazard is the most common type and corresponds to a true data dependence

Answer 184

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 185

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 186

Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution

Answer 187

Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

Answer 188

Exceptions are rare, so simply predicting no exceptions is very accurate

Answer 189

The way in which an object is accessed by a subject

Answer 190

None of them

Answer 191

Speculative operations that don’t cause exceptions

Answer 192

Hardware to check pointer hazards

Answer 193

Speculative operations that don’t cause exceptions

Answer 194

Hardware to check pointer hazards

Answer 195

Pipeline Register File

Answer 196

Physical Register File

Answer 197

Pure Register File

Answer 198

Pending Register File

Answer 199

Fetch, Decode, Instruct, Map, Write

Answer 200

Fetch, Decode, Excite, Memory, Write

Answer 201

Fetch, Decode, Except, Map, Writeback

Answer 202

Fetch, Decode, Execute, Memory, Writeback

Answer 203

Synchronous dynamic random access memory

Answer 204

Static dynamic random access memory

Answer 205

Super dynamic random access memory

Answer 206

Misses in cache / number of instructions

Answer 207

Misses in cache / accesses to cache

Answer 208

Misses in cache / CPU memory accesses

Answer 209

The time from the reception of the response until the user begins to enter the next command

Answer 210

The time for the user to enter the command

Answer 211

The time between when the user enters the command and the complete response is displayed

Answer 212

Hardware technology and organization

Answer 213

Organization and instruction set architecture

Answer 214

Instruction set architecture and compiler technology

Answer 215

The key is stored with the virus

Answer 216

Far more sophisticated techniques are possible

Answer 217

A typical approach is as follows

Answer 218

Infects files that the operating system or shell consider to be executable

Answer 219

Addition Long Accessibility Table

Answer 220

Allocated Link Address Table

Answer 221

Allowing List Address Table

Answer 222

Advanced Load Address Table

Answer 223

Hardware technology and organization

Answer 224

Organization and instruction set architecture

Answer 225

Instruction set architecture and compiler technology

Answer 226

Scaleboard

Answer 227

Scoreboard

Answer 228

Scorebased

Answer 229

0,1,2,3,4,5,6,7

Answer 230

3,4,5,6,7,0,1,2

Answer 231

0,1,2,3,4,5,6,7

Answer 232

3,4,5,6,7,0,1,2

Answer 233

This organization was inspired by applying memory-style errorcorrecting codes to disks

Answer 234

it has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array

Answer 235

Also called mirroring or shadowing, there are two copies of every piece of data

Answer 236

It is the basic element of data

Answer 237

it is a collection of related fields that can be treated as a unit by some application program

Answer 238

it is a collection of related data

Answer 239

it is a collection of similar records

Answer 240

Pipelined caches, multibanked caches, and nonblocking caches

Answer 241

Critical word first and merging write buffer

Answer 242

Small and simple first-level caches and way-prediction

Answer 243

Average length of queue

Answer 244

Average number of tasks in service

Answer 245

Fire, flood, earthquake, power failure and sabotage

Answer 246

Faults in software (usually) and hardware design (occasionally)

Answer 247

Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Answer 248

Address queue

Answer 249

Integer datapath

Answer 250

Allow one instruction to branch multiple directions

Answer 251

Speculative operations that don’t cause exceptions

Answer 252

There are an infinite number of virtual registers available

Answer 253

Branch prediction is perfect, all conditional branches are predicted exactly

Answer 254

Pipelined caches, multibanked caches, and nonblocking caches

Answer 255

Critical word first and merging write buffer

Answer 256

Small and simple first-level caches and way-prediction

Answer 257

The time between when a read is requested and when the desired word arrives

Answer 258

the minimum time between unrelated requests to memory

Answer 259

None of them

Answer 260

exceptions are rare, so simply predicting no exceptions is very accurate

Answer 261

only write architecture state at commit point, so can throw away partially executed instructions after exception

Answer 262

Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

Answer 263

Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads

Answer 264

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 265

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 266

free launch

Answer 267

The time from the reception of the response until the user begins to enter the next command

Answer 268

the time between when the user enters the command and the complete response is displayed

Answer 269

the time for the user to enter the command

Answer 270

Decode instructions, check for data hazard

Answer 271

Decode instructions, check for control hazard

Answer 272

Decode instructions, check for structural hazard

Answer 273

Average length of queue

Answer 274

Average number of tasks in service

Answer 275

All jumps are perfectly predicted

Answer 276

All memory addresses are known exactly

Answer 277

Branch prediction is perfect

Answer 278

Standard Level Offset

Answer 279

Standard Level Objectives

Answer 280

Finished store Buffer

Answer 281

Finished stack Buffer

Answer 282

Finished star Buffer

Answer 283

Finished stall Buffer

Answer 284

Register name

Answer 285

Instruction cache

Answer 286

Data cache

Answer 287

Organization and instruction set architecture

Answer 288

Hardware technology and organization

Answer 289

Instruction set architecture and compiler technology

Answer 290

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Answer 291

Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.

Answer 292

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Answer 293

Random Level Parallelism

Answer 294

Request Level Parallelism

Answer 295

Research Level Parallelism

Answer 296

misses in cache / CPU memory accesses

Answer 297

misses in cache / accesses to cache

Answer 298

misses in cache / number of instructions

Answer 299

Miss Status Handling Register

Answer 300

Memory status handling register

Answer 301

mips status hardware prefetching

Answer 302

map status handling reload

Answer 303

Exploit by remembering the contents of recently accessed locations

Answer 304

Exploit by fetching blocks of data around recently accessed locations

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PCA_Final [arc2-1, Part-1]

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