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NTEN 111 - Midterm 1 Study Guide

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Preperation for NTEN 111 at Okanagan College (2015, Berg)
j.salvino
Quiz por j.salvino, atualizado more than 1 year ago
j.salvino
Criado por j.salvino mais de 8 anos atrás
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Resumo de Recurso

Questão 1

Questão
Which of the following problems would NOT being identified during POST?
Responda
  • memory failure
  • bad monitor
  • bad video card
  • faulty CPU

Questão 2

Questão
In the figure below, Item D is the _______.
Image:
55b444a2-1fee-4466-94d9-b4ad0773de09 (image/jpeg)
Responda
  • system board connections for IDE and floppy drives
  • DIMM slots
  • P1 power connection on the system board
  • PCI local bus slots

Questão 3

Questão
The correct order of the boot process is:
Responda
  • POST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
  • POST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
  • POST, OS configures the system and completes loading, User is able to execute application software
  • POST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS

Questão 4

Questão
What's the first thing the Startup BIOS looks for on a hard drive during boot up?
Responda
  • DOS Boot Record
  • Master Boot Record Correct
  • NT Boot Record
  • Piece of Pie

Questão 5

Questão
POST stands for:
Responda
  • partial operating system test
  • Power-off self test
  • Power-on self test
  • Pre-operational system test
  • None of the above

Questão 6

Questão
Which of the following is NOT a motherboard form factor:
Responda
  • ATX
  • Micro-PTX
  • LPX
  • BTX
  • AT

Questão 7

Questão
Which statement is NOT true about CMOS chips:
Responda
  • They maintain their settings long after you remove the CMOS battery
  • They generally hold between 64 bytes and 512 bytes of memory
  • They are sometimes referred to as NVRAM
  • They contain resource settings for plug-and-play devices in the ESCD
  • They contain the Real Time Clock that holds PC's time and date settings

Questão 8

Questão
How many of the following components are part of the CPU? • ALU • Real Time Clock • branch predictor • Registers • Program Counter
Responda
  • 1
  • 2
  • 3
  • 4
  • 5

Questão 9

Questão
Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?
Responda
  • Doubler and Tripler clocks
  • Derived System Clocks
  • Multiplier and Divider Clocks
  • Frequency Multiplexers

Questão 10

Questão
Which term is commonly used to reference the process of division and multiplication of the system clock to achieve the desired frequency?
Responda
  • Doubler and Tripler clocks
  • Derived System Clocks
  • Multiplier and Divider clocks
  • Frequency Multiplexers

Questão 11

Questão
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
Responda
  • L1
  • L2
  • L3
  • L4

Questão 12

Questão
How many of the following items are true regarding cache? ◦ Cache uses DRAM with is faster that SRAM (found in main memory) ◦ Cache is not always found in the CPU ◦ Cache is designed as temporary storage for the CPU ◦ The size of cache is matched to be equal to the amount of main memory in the computer
Responda
  • 0
  • 1
  • 2
  • 3
  • 4

Questão 13

Questão
Early Pentium CPUs are said to have multi-processing capabilities because they ____________
Responda
  • Can process data coming in while sending data out
  • Have the ability to exist with other processors
  • Use multiple registers
  • Contain two Arithmetic Logic Units Correct

Questão 14

Questão
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
Responda
  • L4
  • L3
  • L2
  • L1

Questão 15

Questão
Different speeds for computer components are achieved by using what is called ___________.
Responda
  • Frequency Multiplexers
  • Multiplier and Divider clocks
  • Derived System Clocks
  • Doubler and Tripler clocks

Questão 16

Questão
Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.
Responda
  • I/O Controller Hub
  • ISA bus
  • Graphics Memory Controller Hub
  • South Bridge

Questão 17

Questão
The amount of addressable memory is determined by the size of the address bus.
Responda
  • True
  • False

Questão 18

Questão
The Multiplier is the term used to describe the ________________
Responda
  • the ratio of the Backside Bus speed to the Memory Bus speed
  • the ratio of the Backside Bus speed to the CPU operating speed
  • the ratio of the CPU operating speed to the Front Side Bus speed
  • the ratio of the PCI bus speed to the Memory Bus speed

Questão 19

Questão
The front side bus connects the CPU to the ______.
Responda
  • coprocessor
  • L1 cache
  • system clock
  • memory bus

Questão 20

Questão
A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump
Responda
  • Control Unit
  • Branch Predictor
  • Hyper-Threading Technology
  • Cache

Questão 21

Questão
A unit that controls the operations of all components in the processor and executes conditional instructions
Responda
  • control unit
  • Instruction Register
  • Branch Predictor
  • ALU

Questão 22

Questão
Allows access to the hard disk drive, USB ports and other I/O devices
Responda
  • Cache
  • Program Counter
  • North Bridge
  • South Bridge

Questão 23

Questão
Allows access to the RAM and video card
Responda
  • North Bridge
  • South Bridge
  • West Bridge
  • East Bridge

Questão 24

Questão
A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel
Responda
  • Cache
  • Arithmetic Logic Unit
  • Hyper-Threading Technology
  • Superscalar Architecture

Questão 25

Questão
An internal memory location that contrains the instruction that is to be executed.
Responda
  • Cache
  • Instruction Register
  • Branch Predictor
  • South Bridge

Questão 26

Questão
The part of the CPU that processes arithmetic and logical instructions
Responda
  • Floating Point Unit
  • Arithmetic Logic Unit
  • Multiplier Bus
  • Divisor Programming Unit

Questão 27

Questão
An internal memory location that contains the address of the next instruction to be executed
Responda
  • Counting Register
  • Address Bus Architecture
  • Address Memory Unit
  • Program Counter

Questão 28

Questão
Used as temporary storage for the CPU
Responda
  • RAM
  • ROM
  • Cache
  • Hard Disk Drive

Questão 29

Questão
The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.
Responda
  • DMA Controller
  • IRQ Controller
  • Chipset
  • Super I/O

Questão 30

Questão
Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)
Responda
  • ISA
  • System
  • AGP
  • Memory
  • VESA-Local Bus
  • PCI

Questão 31

Questão
With 486 and higher CPUs, the cache controller is ________.
Responda
  • attached to the CMOS chip
  • not required, as the CPU itself controls the cache
  • housed on the system board
  • embedded in the CPU chip

Questão 32

Questão
Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.
Responda
  • Fast Bridge
  • ICH
  • North Bridge
  • South Bridge

Questão 33

Questão
Which of the following items relieves the CPU of processing traffic to and from all the buses and controllers on the system board?
Responda
  • IRQ Controller
  • Chipset
  • DMA Controller
  • Super I/O

Questão 34

Questão
The fast end of the Chipset Hub Architecture is still often referred to as the hub's ________.
Responda
  • South Bridge
  • North Bridge
  • ICH
  • East Bridge
  • West Bridge

Questão 35

Questão
How many of the following buses connect to the GMCH in the Accelerated Hub Architecture Chipset? •PCI • System • Memory • AGP • ISA • VESA-Local Bus
Responda
  • 1
  • 2
  • 3
  • 4
  • 5

Questão 36

Questão
Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.
Responda
  • 356
  • 504
  • 768
  • 943

Questão 37

Questão
A SCSI chain must be terminated either by a passive, active or forced perfect terminator.
Responda
  • True
  • False

Questão 38

Questão
With IDE drives, the OS executes the remainder of the format process. This is known as a _____. Select one:
Responda
  • low level format
  • high-level format
  • partition
  • part

Questão 39

Questão
Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.
Responda
  • True
  • False

Questão 40

Questão
Which SCSI ID would usually be used for Hard Drives?
Responda
  • 0
  • 2
  • 4
  • 7

Questão 41

Questão
In a process called _____, track and sector markings are written on the hard drive at the factory.
Responda
  • high-level formatting
  • low level formatting
  • partitioning
  • parking

Questão 42

Questão
IDE drives use a _____-pin cable.
Responda
  • 34
  • 40
  • 50
  • 68

Questão 43

Questão
LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.
Responda
  • True
  • False

Questão 44

Questão
What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?
Responda
  • Parallel ATA
  • Serial ATA
  • Synchronous ATA
  • Single Mode ATA

Questão 45

Questão
Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.
Responda
  • True
  • False

Questão 46

Questão
Zone Bit Recording means ___________________
Responda
  • the number of sectors/track vary depending on the location of the track.
  • the tracks are arranged so the same number of sectors are used for all tracks.
  • each bit is recorded one zone at a time
  • a type of logical method of addressing larger capacity drives

Questão 47

Questão
Serial ports transmit data one byte at a time.
Responda
  • True
  • False

Questão 48

Questão
Which of the following is NOT a type of parallel port?
Responda
  • SPP
  • EPP
  • ECP
  • EDP

Questão 49

Questão
Parallel ports transmit data in parallel, _____ bit(s) at a time.
Responda
  • 1
  • 2
  • 4
  • 8

Questão 50

Questão
When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.
Responda
  • Normal
  • LBA
  • CHS
  • ECHS

Questão 51

Questão
Which of the following is true about SCSI vs EIDE?
Responda
  • EIDE is harder to set up than SCSI
  • SCSI is faster and more expensive
  • EIDE is faster and more expensive
  • SCSI is more popular than EIDE

Questão 52

Questão
The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?
Responda
  • 504 MB
  • 7.88 Gbits
  • 128 GB
  • 7.88 GB

Questão 53

Questão
In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.
Responda
  • adapter
  • ROM bios
  • CMOS chip
  • controller

Questão 54

Questão
The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.
Responda
  • actuators
  • heads
  • platters
  • spindles

Questão 55

Questão
A null-modem cable can be used to directly connect two ____ devices.
Responda
  • DTE
  • DCE
  • DCA
  • DMA

Questão 56

Questão
Which statement is NOT true about CMOS chips:
Responda
  • They maintain their settings long after you remove the CMOS battery
  • They generally hold between 64 bytes and 512 bytes of memory
  • They are sometimes referred to as NVRAM
  • They contain resource settings for plug-and-play devices in the ESCD (Extended System Configuration Data) area
  • The contain the Real Time Clock that holds the PC’s time and date settings

Questão 57

Questão
The fast end of the Chipset Hub Architecture is still often referred to as the hub's ________.
Responda
  • South Bridge
  • North Bridge
  • ICH
  • East Bridge
  • West Bridge

Questão 58

Questão
Parallel ports are only able to transmit data in one direction at any given time.
Responda
  • True
  • False

Questão 59

Questão
Synchronous memory requires an external clock signal while Asynchronous does not.
Responda
  • True
  • False

Questão 60

Questão
How many of the following statements are true? ◦ DRAM is always faster that SRAM ◦ SRAM is lower cost that DRAM ◦ Both DRAM and SRAM are available in synchronous and asynchronous forms ◦ Both SRAM and DRAM retains values when the power is off
Responda
  • 0
  • 1
  • 2
  • 3
  • 4

Questão 61

Questão
How many of the following statements are true? ◦ DRAM does not require refreshing to hold data ◦ SRAM allows for faster data access that DRAM ◦ SRAM costs more than DRAM per byte ◦ SRAM and DRAM memory cells are the same physical size per byte
Responda
  • 0
  • 1
  • 2
  • 3
  • 4

Questão 62

Questão
How many of the following statements are true? ◦ ECC and non-ECC memory cost the same ◦ The parity bit in parity memory can be used to reconstruct bad data ◦ ECC memory allows for the correction of single bit errors ◦ Non-parity memory can detect and correct memory errors
Responda
  • 0
  • 1
  • 2
  • 3
  • 4

Questão 63

Questão
How many of the following statements are true? ◦ ECC and non-ECC memory cost the same ◦ The parity bit in parity memory can be used to reconstruct bad data ◦ ECC memory allows for the correction of single bit errors ◦ Non-parity memory can detect and correct memory errors
Responda
  • Even
  • Odd

Questão 64

Questão
Which BUS version is set to replace AGP?
Responda
  • PCIe
  • ISA
  • Infiniband
  • PCI-X

Questão 65

Questão
With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.
Responda
  • True
  • False

Questão 66

Questão
Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.
Responda
  • True
  • False

Questão 67

Questão
What kind of Parity checking is being used if the following byte of data and it's parity bit are correct: Value: 1011 0111 Parity Bit: 1
Responda
  • even
  • equal
  • odd
  • balanced

Questão 68

Questão
Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.
Responda
  • PRAM, DRAM
  • SRAM, DRAM
  • DRAM, SRAM
  • SRAM, PRAM

Questão 69

Questão
What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?
Responda
  • Ram Timing Detect
  • Auto-Timing Detect
  • Serial Presence Detect
  • Memory Alert

Questão 70

Questão
Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.
Responda
  • True
  • False

Questão 71

Questão
You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?
Responda
  • 1.6GB/s
  • 2.1GB/s
  • 3.2GB/s
  • 1.06GB/s

Questão 72

Questão
One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.
Responda
  • checksum
  • bit parity
  • ESCD
  • PRAM

Questão 73

Questão
What type of bus is displayed in the figure below
Image:
856a0f4c-e3fd-49c5-ac2c-fc939a0a81cb (image/jpeg)
Responda
  • 16-bit ISA
  • VESA
  • 8-bit ISA
  • PCI

Questão 74

Questão
The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus. (HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)
Responda
  • 6,3
  • 3,6
  • 5,3
  • 5,4

Questão 75

Questão
Which of the following is a list of expansion bus types ?
Responda
  • MCA, PCI, Memory
  • ISA, EISA
  • ISA, PCD, AGD
  • PCI, DIMM, SIMM

Questão 76

Questão
The ______ ISA bus was so named because it had only an eight-bit data path.
Responda
  • 4-bit
  • 8-bit
  • 16-bit
  • 32-bit

Questão 77

Questão
ECC may be present on DIMM module, and correct single bit errors when possible.
Responda
  • True
  • False

Questão 78

Questão
DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.
Responda
  • True
  • False

Questão 79

Questão
Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.
Responda
  • even
  • equal
  • odd
  • balanced

Questão 80

Questão
All data stored in _____ is lost when the power is turned off.
Responda
  • PRAM
  • RAM
  • ROM
  • CMOS

Questão 81

Questão
On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)
Responda
  • 2.1 GB/s
  • 1.6 GB/s
  • 500 MB/s
  • 3.2 GB/s

Questão 82

Questão
The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.
Responda
  • S-100
  • 8-bit ISA
  • 16-bit ISA
  • EISA

Questão 83

Questão
ECC RAM differs from parity and nonparity RAM in that it can ______.
Responda
  • retain data when the power is removed
  • detect errors
  • automatically save data to the hard drive
  • detect and potentially correct errors

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