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[Final Study] Unit 2 Pipelined CPU

Descrição

Unit 2 of UBC's CS313 course. Get some alcohol.
Zim Brightwood
Quiz por Zim Brightwood, atualizado more than 1 year ago
Zim Brightwood
Criado por Zim Brightwood mais de 7 anos atrás
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Resumo de Recurso

Questão 1

Questão
Throughput is
Responda
  • the rate at which instructions leave the pipeline
  • total time it takes an instruction to be processed by a stage
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by the entire pipeline

Questão 2

Questão
Latency is
Responda
  • total time it takes an instruction to be processed by the entire pipeline
  • the rate at which instructions leave the pipeline
  • the rate at which instructions move to the next register
  • total time it takes an instruction to be processed by a stage

Questão 3

Questão
Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
Responda
  • Throughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
  • Throughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
  • Throughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up

Questão 4

Questão
Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
Responda
  • between each stage
  • after each stage
  • before each stage
  • inputs for that stage
  • outputs for that stage
  • inputs for the next stage
  • in parallel
  • sequentially

Questão 5

Questão
And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
Responda
  • in flight
  • executing
  • latent
  • active
  • retired
  • finished
  • complete
  • ready

Questão 6

Questão
The pipeline instructions are executed in order
Responda
  • True
  • False

Questão 7

Questão
Instruction-level parallelism exists between a pair of instructions if
Responda
  • their execution order does not matter
  • their execution order matters

Questão 8

Questão
The pipeline requires some parallelism
Responda
  • True
  • False

Questão 9

Questão
Dependencies exist if execution order doesn't matter
Responda
  • True
  • False

Questão 10

Questão
Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
Responda
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;
  • B write to a location read by A Example: b = a; a = 1;

Questão 11

Questão
Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
Responda
  • B write to visible location written by A Example: a = 1; a = 2;
  • B reads value written by A Example: a = 1; b = a;
  • B write to a location read by A Example: b = a; a = 1;

Questão 12

Questão
Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
Responda
  • B write to a location read by A Example: b = a; a = 1;
  • B reads value written by A Example: a = 1; b = a;
  • B write to visible location written by A Example: a = 1; a = 2;

Questão 13

Questão
[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
Responda
  • Expressing
  • Adding
  • Mechanizing
  • Conflating
  • Eating
  • Exploiting
  • Removing
  • Smelling
  • Tangential Execution

Questão 14

Questão
A pipeline hazard exists when
Responda
  • the processor's execution would violate a data or control dependency
  • the processor's execution would support a data or control dependency
  • the processor's execution would cause a data or control dependency
  • the processor's execution would execute a data or control dependency

Questão 15

Questão
We should detect pipeline hazards
Responda
  • True
  • False

Questão 16

Questão
Stalling is one way to handle pipeline hazards
Responda
  • True
  • False

Questão 17

Questão
A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle. A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.
Responda
  • pipeline stall
  • pipeline bubble
  • pipeline hazard
  • pipeline stage
  • pipeline overhead

Questão 18

Questão
The only data hazards in the Y86 Pipeline are causal hazards on register file
Responda
  • True
  • False

Questão 19

Questão
The only control hazards in the Y86 Pipeline are conditional jumps
Responda
  • True
  • False

Questão 20

Questão
To prevent a data hazard by stalling, we can
Responda
  • read registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
  • read registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
  • read registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired

Questão 21

Questão
How would we resolve a conditional jump control hazard by stalling?
Responda
  • stall fetch until jump exits execute
  • stall execute until jump exits decode
  • stall fetch and execute until jump exits decode
  • stall fetch, decode, and execute until jump exits memory
  • stall fetch, decode, execute, and memory until jump exits write back
  • just stall everything after fetch indefinitely and go finish off a bottle of wine in one go

Questão 22

Questão
How would we resolve a return control hazard by stalling?
Responda
  • stall fetch until return exits memory
  • stall decode until return exits memory
  • stall fetch and decode until return exits memory
  • stall fetch, decode, and execute until return exits memory
  • stall fetch, decode, execute, and memory until return exits memory
  • return to cpsc313 in the summer after you fail this midterm

Questão 23

Questão
Check all the statements that are true about the pipeline-control module
Responda
  • it's a hardware component separate from the 5 stages
  • examines values across every stage
  • decides whether stage should stall or bubble

Questão 24

Questão
Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
Responda
  • True
  • False

Questão 25

Questão
Where does data forwarding forward its data to?
Responda
  • D
  • W
  • M
  • E
  • F

Questão 26

Questão
Where does data forward forward its data from?
Responda
  • W - new value from memory or ALU
  • M - new value read from memory or from ALU
  • E - new value from ALU
  • D - new value from registers
  • F - new value from PC determined instruction

Questão 27

Questão
Which of these are data hazards?
Responda
  • register-register hazard
  • load-use hazard
  • register-memory hazard
  • memory-memory hazard
  • use-use hazard
  • load-load hazard

Questão 28

Questão
Which of these is a register-register hazard?
Responda
  • irmovl $1, %eax addl %eax, %ebx
  • irmovl $1, %ecx addl %eax, %ebx

Questão 29

Questão
How do we handle a register-register hazard with data forwarding?
Responda
  • forward to D from E, M, or W
  • forward to F from E, M, or W
  • stall one cycle, then forward to D from E, M, or W
  • stall one cycle, then forward to F from D, E, M, or W
  • stall one cycle, then forward to F from E, M, or W
  • forward to F from D, E, M, or W

Questão 30

Questão
Which of these is a load-use hazard?
Responda
  • mrmovl (esi), %eax addl %eax, %ebx
  • rmmovl %eax, (esi) addl %eax, %ebx

Questão 31

Questão
How would we handle a load-use hazard?
Responda
  • Stall use one cycle, forward to D from M or W
  • Stall use one cycle, forward to D from E or M
  • Stall use one cycle, forward to E from D, M, or W
  • Stall use one cycle, forward to E from M or W

Questão 32

Questão
Jump prediction is not suitable for resolving conditional-jump hazards
Responda
  • True
  • False

Questão 33

Questão
We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
Responda
  • E
  • D
  • M
  • W

Questão 34

Questão
valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
Responda
  • not taken
  • taken

Questão 35

Questão
When a mis-predicted jump is in M, what should we do?
Responda
  • shootdown D and E to prevent them from doing damage
  • shootdown F and D to prevent them from doing damage
  • shootdown M and W to prevent them from doing damage

Questão 36

Questão
The homework in this course is much too long
Responda
  • True
  • False

Questão 37

Questão
We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
Responda
  • True
  • False

Questão 38

Questão
We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
Responda
  • True
  • False

Questão 39

Questão
In regards to static jump prediction, what could the compiler know?
Responda
  • a jump's taken tendency
  • for loops, it can decide to use a continue condition or exit condition
  • for if statements it might be able to spot error tests
  • what it sees in the program text

Questão 40

Questão
The compiler cares about the ISA's jump predictions
Responda
  • True
  • False

Questão 41

Questão
How do we optimize handling the return hazard?
Responda
  • Keep a stack of return addresses for future use
  • Guess the return address based on the value in predPC
  • Guess the return address based on the value in PC
  • Guess the return address based on the valP in D

Questão 42

Questão
Y86 has indirect jumps
Responda
  • True
  • False

Questão 43

Questão
Indirect jumps are needed for polymorphic dispatch
Responda
  • True
  • False

Questão 44

Questão
CPI =
Responda
  • totalCycles / instructionRetiredCycles
  • instructionRetiredCycles / totalCycles

Questão 45

Questão
What are the tendencies of deeper pipelines?
Responda
  • reduce clock period
  • increase CPI
  • makes stalling harder to avoid

Questão 46

Questão
Which of these are attributes of super-scalar?
Responda
  • multiple pipelines that run in parallel
  • issue multiple instructions on each cycle
  • instructions execute in parallel and can even bypass each other
  • if I shut my eyes tight enough, will the midterm disappear?

Questão 47

Questão
What does hyper-threading consist of? (Only one of the following is correct)
Responda
  • OS loads multiple runnable threads into CPU, usually from the same process
  • CPU does fast switching between threads to hide memory latency

Questão 48

Questão
What is multi-core?
Responda
  • multiple CPUs per chip, each pipelined, super-scalar, etc
  • CPU's execute independent threads from possibly different processes

Questão 49

Questão
How could Mike do this to us?
Responda
  • Sadism
  • Also sadism
  • And sadism
  • All of the above

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