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Perguntas do quiz (54)
1Which of the following descriptions corresponds to static power?
- AProportional to the product of the number of switching transistors and the switching rate
- BGrows proportionally to the transistor count (whether or not the transistors are switching)
- CDominant energy consumer
- DAll of the above
2Which of the following descriptions corresponds to dynamic power?
- AProportional to the product of the number of switching transistors and the switching rate
- BGrows proportionally to the transistor count (whether or not the transistors are switching)
- CCertainly a design concern
- DNone of the above
3Which of the written below is NOT increase power consumption?
- AIncreasing performance
- BIncreasing multiple cores
- CIncreasing multithreading
- DDecreasing performance
4Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when
- AThe number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
- BThe number of transistors switching will be proportional to the sustained rate, and the performance is proportional to the peak issue rate
- CThe number of transistors switching will be proportional to the sustained rate
- DThe performance is proportional to the peak issue rate
5How this process called: “Operations execute as soon as their operands are available”
- Adata flow execution
- Binstruction execution
- Cdata control execution
- Dinstruction field execution
6If we want to sustain four instructions per clock
- AWe must fetch less, issue more, and initiate execution on more than two instructions
- BWe must fetch more, issue less, and initiate execution on more than three instructions
- CWe must fetch more, issue more, and initiate execution on more than four instructions
- DWe must fetch more, issue more, and initiate execution on less than five instructions
7For what the reorder buffer is used :
- ATo pass parameters through instructions that may be speculated
- BTo pass results among instructions that may be speculated.
- CTo get additional registers in the same way as the reservation stations
- DTo control registers
8How many fields contains the entry in the ROB:
- A5
- B6
- C3
- D4
9Choose correct fields of entry in the ROB:
- Athe source type, the destination field, the value field, and the ready field
- Bthe program type, the ready field, the parameter field, the destination field
- Cthe instruction type, the destination field, the value field, and the ready field
- Dthe instruction type, the destination field, and the ready field
10Choose the steps of instruction execution:
- Aissue, execute, write result, commit
- Bexecution, commit, rollback
- Cissue, execute, override, exit
- Dbegin, write, interrupt, commit
11Which Multiple-issue processors has not the hardware hazard detection:
- ASuperscalar(dynamic)
- BSuperscalar(static)
- CSuperscalar(speculative)
- DEPIC
12Examples of EPIC:
- APentium 4, MIPS R12K, IBM, Power5
- BItanium
- CMIPS and ARM
- DTI C6x
13Examples of superscalar(static):
- APentium 4, MIPS R12K, IBM, Power5
- BItanium
- CMIPS and ARM
- DTI C6x
14If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
- AStatic power
- BDynamic power
- CProcessing rate
- DProcessor state
15Examples of superscalar(dynamic) :
- APentium 4, MIPS R12K, IBM, Power5
- BNone at the present
- CMIPS and ARM
- DTI C6x
16When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
- AStatic power
- BDynamic power
- CProcessing rate
- DProcessor state
17Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
- ALimited ILP due to software dependences
- BAchievable ILP with hardware resource constraints
- CVariability of ILP due to software and hardware interaction
- DAchievable ILP with software resource constraints
18Examples of VLIW/LIW:
- APentium 4, MIPS R12K, IBM, Power5
- BItanium
- CMIPS and ARM
- DTI C6x
19What is a hash table?
- APopular data structure for updating large collections, so that one can hardly answer questions
- BPopular tables for organizing a large collection of data structure
- CPopular data structure for organizing a large collection of data items so that one can quickly answer questions
- DPopular data structure for deleting small collections of data items so that one can hardly answer questions
20A branch-prediction cache that stores the predicted address for the next instruction after a branch
- Abranch-target buffer
- Bdata buffer
- Cframebuffer
- Doptical buffer
21Buffering the actual target instructions allows us to perform an optimization which called:
- Abranch folding
- BBranch prediction
- CTarget instructions
- DTarget address
22Which of these is NOT characteristics of recent highperformance microprocessors?
- APower
- BFunctional unit capability
- CClock rate
- DColor
23Which is not the function of integrated instruction fetch unit:
- AIntegrated branch prediction
- BInstruction prefetch
- CInstruction memory access and buffering
- DInstruction memory commit
24What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
- AAddress aliasing prediction
- BBranch prediction
- CIntegrated branch prediction
- DDynamic branch prediction
25How to decrypt RISC?
- AReduced Instruction Set Computer
- BRecall Instruction Sell Communication
- CRename Instruction Sequence Corporation
- DRed Instruction Small Computer
26The ideal pipeline CPI is a measure of …
- Athe maximum performance attainable by the instruction
- Bthe minimum performance attainable by the implementation
- Cthe maximum performance attainable by the implementation
- Dthe minimum performance attainable by the instruction
27what is the Pipeline CPI = ?
- Adeal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
- Bdeal pipeline CPU + Data hazard stalls + Control stalls
- Cdeal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
- DStructural stalls + Data hazard stalls + Control stalls
28The simplest and most common way to increase the ILP is …?
- Ato exploit minimalism among iterations of a loop
- Bto exploit parallelism among iterations of a loop
- Cto destroy iterations of a loop
- Dto decrease the minimalism of risk
29The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
- Aexploit-level parallelism
- Bhigh-level minimalism
- Cloop-level parallelism
- Dlow-level minimalism
30In parallelism have three different types of dependences, tagging him:
- Adata dependences , name dependences , and control dependences .
- Bdata dependences , name dependences , and surname dependences .
- Cdatagram dependences , name dependences , and animal dependences .
- Dno correct answers
31What is Name dependence?
- Aname dependence occurs when two instructions use the same register or memory location
- Bname dependence occurs when five or more instructions use the same register or memory location
- Cname dependence occurs when instructions use the same name
- DAll answers is correct
32When occurs an output dependence?
- Awhen i and instruction j write the same name
- Bwhen i and instruction j write the same register or memory location
- Cwhen i and instruction j write the same adress or memory location
- DAll answers is correct
33What is RAW (read after write)?
- Awhen j tries to read a source before i writes it, so j incorrectly gets the old value
- Bwhen i tries to read a source before j writes it, so j correctly gets the old value
- Cwhen j tries to write a source before i writes it
- Dwhen a tries to write a source before b read it, so a incorrectly gets the old value
34What is given is not a hazard?
- AWAR
- BRAR
- CWAW
- DLOL
35A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
- Aloop-level
- BRAR
- Cloop rolling
- Dloop unrolling
36Effect that results from instruction scheduling in large code segments is called…?
- Aloop unrolling
- Bloop-level
- Cregister pressure
- Dregistration
37The simplest dynamic branch-prediction scheme is a
- Abranch-prediction buffer
- Bbranch buffer
- CAll answers correct
- Dno correct answers
38Branch predictors that use the behavior of other branches to make a prediction are called
- Acorrelating predictors or two-level predictors
- Bbranch-prediction buffer
- Cbranch table
- Dthree level loop
39How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
- Athe number of prediction entries selected by the branch = 1K.
- Bthe number of prediction entries selected by the branch = 2K.
- Cthe number of prediction entries selected by the branch = 8K.
- Dthe number of prediction entries selected by the branch = 4K.
40What is the compulsory in Cs model?
- AThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- BIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- CThe number of accesses that miss divided by the number of accesses.
- DNone of these
41What is capacity in Cs model?
- AIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- CThe number of accesses that miss divided by the number of accesses.
- DNone of these
42What is conflict in Cs model?
- AIf the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
- BThe very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
- CIf the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
- DNone of these
43Choose the benefit of Cache Optimization.
- ALarger block size to reduce miss rate
- BBigger caches to increase miss rat
- CSingle level caches to reduce miss penalty
- DNone of these
44Choose the strategy of Seventh Optimization.
- ACritical word first
- BCritical restart
- CSequential interleaving
- DMerging Write Buffer to Reduce Miss Penalty
45Choose the Eight Optimization
- AMerging Write Buffer to Reduce Miss Penalty
- BCritical word first
- CNonblocking Caches to Increase Cache Bandwidth
- DTrace Caches to Reduce Hit Time
46Choose the Eleventh Optimization
- ACompiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
- BMerging Write Buffer to Reduce Miss Penalty
- CHardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
- DNone of these
47What is the access time?
- ATime between when a read is requested and when the desired word arrives
- BThe minimum time between requests to memory.
- CDescribes the technology inside the memory chips and those innovative, internal organizations
- DNone of these
489. What is the cycle time?
- AThe minimum time between requests to memory.
- BTime between when a read is requested and when the desired word arrives
- CThe maximum time between requests to memory.
- DNone of these
49What does SRAM stands for?
- AStatic Random Access memory
- BSystem Random Access memory
- CShort Random Access memory
- DNone of these
50What does DRAM stands for?
- ADynamic Random Access memory
- BDual Random Access memory
- CDataram Random Access memory
- DNone of these
51What does DDR stands for?
- ADouble data rate
- BDual data rate
- CDouble data reaction
- DNone of these
52What is kernel process?
- AProvide at least two modes, indicating whether the running process is a user process or an operating system process
- BProvide at least five modes, indicating whether the running process is a user process or an operating system process
- CProvide a portion of the processor state that a user process can use but not write
- DNone of these
53Which one is NOT concerning to pitfall?
- ASimulating enough instructions to get accurate performance measures of the memory hierarchy
- BImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- COveremphasizing memory bandwidth in DRAMs
- DPredicting cache performance of one program from another
54Which one is concerning to fallacy?
- ASimulating enough instructions to get accurate performance measures of the memory hierarchy
- BPredicting cache performance of one program from another
- CImplementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- DOveremphasizing memory bandwidth in DRAMs
Informações
- Descrição
- It always seems impossible until it’s done.
- Autor
- Csse 1502
- Idioma
- English
- Visualizações
- 52
- Etiquetas
- Avaliação
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