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Good Guy Beket
Quiz by Good Guy Beket, updated more than 1 year ago
Good Guy Beket
Created by Good Guy Beket over 6 years ago
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Question 1

Question
In 32-bit addressing mode, address field is either 1 byte or?
Answer
  • 4 bytes
  • 2 bytes
  • 6 bytes

Question 2

Question
If a block can be placed at every location in cache, this cache is said to be?
Answer
  • Fully associative
  • Directly mapped
  • Indirectly mapped

Question 3

Question
Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?
Answer
  • Write-through
  • Write-back
  • Miss rate

Question 4

Question
Average access time of memory for having memory-hierarchy performance is given as?
Answer
  • Average memory access time = Hit time - Miss rate
  • Average memory access time = Hit time + (miss rate and miss penalty)
  • Average memory access time = Hit time + Miss rate - Miss penalty

Question 5

Question
As segment or a page is normally used for block, page-fault and address-fault is used for:
Answer
  • Hit
  • Miss
  • Cache
  • Stack

Question 6

Question
Virtual memory producing virtual-addresses, are translated by:
Answer
  • Logical addresses
  • Physical addresses
  • Local addresses
  • All above

Question 7

Question
Per memory reference, miss-rate can be turned into per instruction misses rate by
Answer
  • Miss rate= Memory accesses* instructions
  • Miss rate= Memory accesses/ instructions
  • Miss rate= Memory accesses-instructions
  • Miss rate= Memory accesses+ instructions

Question 8

Question
Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
Answer
  • Read back
  • Cache miss
  • Virtual memory
  • Cache hit

Question 9

Question
For reducing frequency on replacement of write-back blocks, commonly used feature, is known as:
Answer
  • Hit miss
  • Index field
  • Dirty bit
  • Write-through

Question 10

Question
If cache is not able for containing all blocks needed while execution, miss is then known as
Answer
  • Hit miss
  • Cache hit
  • Cache miss (capacity miss)
  • Hit rate

Question 11

Question
For completing programmer's desire for unlimited quick memory, suggested economical solution was:
Answer
  • Memory hierarchy
  • Temporal locality
  • Spatial locality

Question 12

Question
An instruction that does no operation for changing state is known as
Answer
  • Nope
  • No
  • NOP

Question 13

Question
Set of instructions examined as candidates for potential execution is called the
Answer
  • Frame
  • Cube
  • Window

Question 14

Question
Term 'computer architecture' is sometimes referred only to:
Answer
  • Instruction set design
  • Circuit design
  • Hardware design

Question 15

Question
General categories of instructions' operation are
Answer
  • Data transfer
  • Arithmetic logical
  • floating point
  • All above

Question 16

Question
The effectiveness of the cache memory is based on the property of:
Answer
  • Locality of reference
  • Memory localization
  • Memory size

Question 17

Question
The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
Answer
  • Level 2 cache
  • Level 1 cache
  • Registers

Question 18

Question
The last on the hierarchy scale of memory devices is ______.
Answer
  • Main memory
  • Branch
  • Secondary memory

Question 19

Question
A common measure of performance is
Answer
  • Price/performance ratio.
  • Performance/price ratio
  • Operation/price ratio.

Question 20

Question
The number successful accesses to memory stated as a fraction is called as _____
Answer
  • Miss rate
  • Hit rate
  • Access rate

Question 21

Question
With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as:
Answer
  • Scalability
  • Module availability
  • Module reliability

Question 22

Question
From a reference initial instant, a measure of service accomplishment, is known as:
Answer
  • Module reliability
  • Hardware
  • Sector

Question 23

Question
To initialize any port as an output port what value is to be given to it?
Answer
  • 0xFF
  • 0x00
  • 0x01
  • A port is by default an output port

Question 24

Question
In AVR, which registers are there for the I/O programming of ports?
Answer
  • all above
  • PORT
  • PIN
  • DDR

Question 25

Question
The data will not go from the port registers to the pin unless:
Answer
  • DDR register of that port is set to 0
  • DDR register of that port is set to 1
  • PORT register of that port is set to 0

Question 26

Question
What is the file extension that is loaded in a micro controller for executing any instruction?
Answer
  • .doc
  • .hex
  • .txt

Question 27

Question
What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?
Answer
  • True sharing misses
  • False sharing misses

Question 28

Question
What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
Answer
  • False sharing misses
  • True sharing misses

Question 29

Question
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?
Answer
  • One or more processors have the block cached, and the value in memory is up to date
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • No processor has a copy of the cache block

Question 30

Question
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?
Answer
  • No processor has a copy of the cache block
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • One or more processors have the block cached, and the value in memory is up to date

Question 31

Question
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Uncached” in a simple protocol?
Answer
  • No processor has a copy of the cache block
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • One or more processors have the block cached, and the value in memory is up to date

Question 32

Question
In Non-Blocking Caches what does mean “Early restart”?
Answer
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Question 33

Question
What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • n loop iterations
  • subroutine call
  • vector access

Question 34

Question
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • subroutine call
  • n loop iterations
  • vector access

Question 35

Question
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Answer
  • subroutine call
  • n loop iterations
  • vector access

Question 36

Question
What is kernel process?
Answer
  • Provide at least two modes, indicating whether the running process is a user process or an operating system process
  • Provide at least five modes, indicating whether the running process is a user process or an operating system process
  • Provide a portion of the processor state that a user process can use but not write
  • None of them

Question 37

Question
Which one is NOT concerning to pitfall?
Answer
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Question 38

Question
Which one is concerning to fallacy?
Answer
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Question 39

Question
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Answer
  • Speculative operations that don’t cause exceptions
  • Hardware to check pointer hazards

Question 40

Question
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Answer
  • Hardware to check pointer hazards
  • Speculative operations that don’t cause exceptions

Question 41

Question
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Answer
  • Allow one instruction to branch multiple directions
  • Speculative operations that don’t cause exceptions

Question 42

Question
In Multilevel Caches “Local miss rate” equals =
Answer
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses
  • misses in cache / number of instructions

Question 43

Question
In Multilevel Caches “Global miss rate” equals =
Answer
  • misses in cache / CPU memory accesses
  • misses in cache / accesses to cache
  • misses in cache / number of instructions

Question 44

Question
In Multilevel Caches “Misses per instruction” equals =
Answer
  • misses in cache / number of instructions
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses

Question 45

Question
The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Answer
  • latency
  • bandwidth
  • throughput
  • performance

Question 46

Question
Total amount of work done in a given time , such as megabytes per second for disk transfer...
Answer
  • bandwidth (throughput)
  • latency
  • performance

Question 47

Question
Products that are sold by multiple vendors in large volumes and are essentially identical
Answer
  • commodities
  • boxes
  • folders
  • files

Question 48

Question
Integrated circuit processes are characterized by the:
Answer
  • feature size
  • permanent size n
  • complex size
  • fixed size

Question 49

Question
Manufacturing costs that decrease over time are ____
Answer
  • the learning curve
  • the cycled line
  • the regular option
  • the final loop

Question 50

Question
Volume is a ________ key factor in determining cost.
Answer
  • second
  • first
  • fifth
  • third

Question 51

Question
The most companies spend only ____________ of their income on R&D, which includes all engineering.
Answer
  • 4% to 12%
  • 15% to 30%
  • 1% to 17%
  • 30% to 48%

Question 52

Question
Desktop benchmarks divide into __ broad classes:
Answer
  • two
  • three
  • four
  • five

Question 53

Question
A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Answer
  • 90% 10%
  • 50% 50%
  • 70% 30%
  • 89% 11%

Question 54

Question
(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Answer
  • Speedup
  • Efficiency
  • Probability
  • Ration

Question 55

Question
Which of the following descriptions corresponds to static power?
Answer
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Proportional to the product of the number of switching transistors and the switching rate Probability
  • Proportional to the product of the number of switching transistors and the switching rate
  • All of the above

Question 56

Question
If we want to sustain four instructions per clock
Answer
  • We must fetch more, issue more, and initiate execution on more than four instructions
  • We must fetch less, issue more, and initiate execution on more than two instructions
  • We must fetch more, issue less, and initiate execution on more than three instructions
  • We must fetch more, issue more, and initiate execution on less than five instructions

Question 57

Question
What is a hash table?
Answer
  • Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • Popular data structure for updating large collections, so that one can hardly answer questions
  • Popular tables for organizing a large collection of data structure
  • Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Question 58

Question
How this process called: “Operations execute as soon as their operands are available”
Answer
  • data flow execution
  • instruction execution
  • data control execution
  • instruction field execution

Question 59

Question
For what the reorder buffer is used :
Answer
  • To pass results among instructions that may be speculated.
  • To pass parameters through instructions that may be speculated
  • To get additional registers in the same way as the reservation stations
  • To control registers

Question 60

Question
Which one is not the major flavor of Multiple-issue processors:
Answer
  • statistically superscalar processors
  • dynamically scheduled superscalar processors
  • statically scheduled superscalar processors
  • VLIW (very long instruction word) processors

Question 61

Question
Examples of superscalar(static):
Answer
  • MIPS and ARM
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • TI C6x

Question 62

Question
Examples of superscalar(dynamic) :
Answer
  • None at the present
  • Pentium 4, MIPS R12K, IBM, Power5
  • MIPS and ARM
  • TI C6x

Question 63

Question
Examples of VLIW processor:
Answer
  • TI C6x
  • MIPS and ARM
  • Itanium
  • Pentium 4, MIPS R12K, IBM, Power5

Question 64

Question
Which is not the function of integrated instruction fetch unit:
Answer
  • Instruction memory commit
  • Integrated branch prediction
  • Instruction prefetch
  • Instruction memory access and buffering

Question 65

Question
In the memory hierarchy, as the speed of operation increases the memory size also increases:
Answer
  • True
  • False

Question 66

Question
At VLIW by “performance and loop iteration” which time is longer?
Answer
  • Loop Unrolled
  • Software Pipelined

Question 67

Question
At VLIW by “performance and loop iteration” which time is shorter?
Answer
  • Software Pipelined
  • Loop Unrolled

Question 68

Question
What is a topology in interconnection networks?
Answer
  • It indicates how the nodes a network are organised
  • It is the minimum distance between the farthest nodes in a network
  • Number of edges connected with a node is called node degree

Question 69

Question
What is a Network Diameter?
Answer
  • It is the minimum distance between the farthest nodes in a network
  • It indicates how the nodes a network are organized
  • Number of edges connected with a node is called node degree

Question 70

Question
What is a Node degree?
Answer
  • Number of edges connected with a node
  • It indicates how the nodes a network are organized
  • It is the minimum distance between the farthest nodes in a network

Question 71

Question
What is a Bisection Bandwidth?
Answer
  • Number of edges required to be cut to divide a network into two halves
  • It indicates how the nodes a network are organized
  • It is the minimum distance between the farthest nodes in a network

Question 72

Question
What is Latency?
Answer
  • It indicates how the nodes a network are organized
  • It is the delay in transferring the message between two nodes
  • It is the minimum distance between the farthest nodes in a network

Question 73

Question
What is a Hardware Cost?
Answer
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed established the path between the source and the destination
  • It refers to the cost involved in the implementation of an interconnection network
  • It is an indicative measure of the message carrying capacity of a network

Question 74

Question
What is a Blocking and Non-Blocking network?
Answer
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed establishe the path between the source and the destination
  • In non-blocking networks the route from any free input node to any free output node can always be provided
  • It is an indicative measure of the message carrying capacity of a network

Question 75

Question
Design issue of interconnection network
Answer
  • Software Cost
  • Hardware Cost
  • RLP
  • Symmetry of the network

Question 76

Question
What is a Data transfer time?
Answer
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed established the path between the source and the destination
  • How long does it take for a message to reach to another processor
  • It is an indicative measure of the message carrying capacity of a network

Question 77

Question
Select non-blocking interconnection network
Answer
  • Linear Array
  • Cube
  • CrossBar

Question 78

Question
A modified version of the tree interconnection network
Answer
  • Fat tree
  • Cube
  • Linear Array

Question 79

Question
An interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
Answer
  • Systolic Array
  • Cube
  • Linear Array

Question 80

Question
A _____________ interconnection network is an extension of cube network
Answer
  • Hyper Cube
  • Cube
  • Linear Array

Question 81

Question
In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
Answer
  • Multithreading
  • Computing
  • Array processing

Question 82

Question
Single Instruction, Single Data (SISD):
Answer
  • Only one instruction stream is being acted on by the CPU during any one clock cycle
  • A type of parallel computer
  • Currently, the most common type of parallel computer - most modern supercomputers fall into this category

Question 83

Question
Pipelining …
Answer
  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
  • A logically discrete section of computational work
  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory

Question 84

Question
Shared Memory…
Answer
  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
  • A logically discrete section of computational work
  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line

Question 85

Question
What is a RISC computers?
Answer
  • Reduced Instruction Set Computer
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer

Question 86

Question
When single-processor performance improvement has dropped?
Answer
  • 2003
  • 2004
  • 2002

Question 87

Question
How much in percentage single-processor performance improvement has dropped to less than?
Answer
  • 22%
  • 11%
  • 33%

Question 88

Question
How many classes of computers classified?
Answer
  • 3
  • 5
  • 7

Question 89

Question
What is the PMD in computer classes?
Answer
  • Percentage map device
  • Powerful markup distance
  • Peak maze development
  • Personal mobile device

Question 90

Question
What is the Thread Level Parallelism?
Answer
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Question 91

Question
What is the Request Level Parallelism:
Answer
  • o Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Question 92

Question
What is the Instruction Level Parallelism:
Answer
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Question 93

Question
What is the MISD one of the categories of computers?
Answer
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instruction Streams, Set Data Stream

Question 94

Question
How many elements in Trends of Technology?
Answer
  • 5
  • 4
  • 6

Question 95

Question
How many elements of the Instruction Set Architecture (ISA):
Answer
  • 7
  • 8

Question 96

Question
How many types of dependencies do you know?
Answer
  • 3
  • 4
  • 5

Question 97

Question
How many possible Elements of Data Hazards?
Answer
  • 3
  • 6
  • 8

Question 98

Question
What is the “ISSUE” in Pipelining Basics?
Answer
  • Decode instructions, check for structural hazard
  • Decode instructions, check for data hazard
  • Decode instructions, check for control hazard

Question 99

Question
What is the “Read Operands” in Pipelining Basics?
Answer
  • Wait until no data hazards, then read operands
  • Wait until no control hazards, then read operands
  • Wait until no structural hazards, then read operands

Question 100

Question
How many Optimizations’ in Cache memory Performance?
Answer
  • 10
  • 8
  • 6

Question 101

Question
What is the Compulsory in main categories in Cache Memory?
Answer
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Question 102

Question
What is the Capacity in main categories in Cache Memory?
Answer
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Question 103

Question
What is the Conflict in main categories in Cache Memory?
Answer
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Question 104

Question
What is the Temporal Locality?
Answer
  • Exploit by remembering the contents of recently accessed locations
  • Exploit by fetching blocks of data around recently accessed locations

Question 105

Question
What is the Spatial Locality?
Answer
  • Exploit by fetching blocks of data around recently accessed locations
  • Exploit by remembering the contents of recently accessed locations

Question 106

Question
What is the Reducing the Hit time?
Answer
  • Small and simple first-level caches and way-prediction
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Critical word first and merging write buffer

Question 107

Question
What is the Increasing cache bandwidth?
Answer
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Small and simple first-level caches and way-prediction
  • Critical word first and merging write buffer

Question 108

Question
What is the Reducing the Miss Penalty?
Answer
  • Critical word first and merging write buffer
  • Small and simple first-level caches and way-prediction
  • Pipelined caches, multibanked caches, and nonblocking caches

Question 109

Question
What is the Reducing the Miss Rate?
Answer
  • Compiler Optimization
  • Time Optimization
  • Performance Optimization

Question 110

Question
Main term of dependability is SLAs?
Answer
  • Service level agreements
  • Standard level achievement
  • Scale level approach

Question 111

Question
Main term of dependability is SLOs?
Answer
  • Service level objectives
  • Standard level offset

Question 112

Question
The second type of dependence is?
Answer
  • Name dependence
  • Data dependence
  • Control dependence

Question 113

Question
RAW (read after write)?
Answer
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard corresponds to an output dependence
  • This hazard arises from an antidependence (or name dependence)

Question 114

Question
WAW (write after write)?
Answer
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard arises from an antidependence (or name dependence)

Question 115

Question
WAR (write after read)?
Answer
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard arises from an antidependence (or name dependence)

Question 116

Question
What is the element “Read Operands” in simple five-stage pipeline?
Answer
  • Decode instructions, check for structural hazards
  • Wait until no data hazards, then read operands

Question 117

Question
What is the ROB?
Answer
  • Reorder buffer
  • Read only buffer
  • Relocate buffer

Question 118

Question
How many steps in instruction execution?
Answer
  • 6
  • 5
  • 3
  • 4

Question 119

Question
How many restrictions RAW hazards through memory are maintained?
Answer
  • 2
  • 3
  • 4

Question 120

Question
How many major flavors in Multiple-issue processors?
Answer
  • 3
  • 4
  • 5

Question 121

Question
How many functions at Integrated Instruction Fetch Units
Answer
  • 3
  • 4
  • 5

Question 122

Question
Speculation and the Challenge of Energy Efficiency consume excess energy in how many ways?
Answer
  • 2
  • 3
  • 4

Question 123

Question
The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
Answer
  • 5
  • 4
  • 6

Question 124

Question
Infinite register renaming at The Hardware Model?
Answer
  • There are an infinite number of virtual registers available
  • Branch prediction is perfect, all conditional branches are predicted exactly

Question 125

Question
Perfect Branch Prediction at the Hardware Model?
Answer
  • There are an infinite number of virtual registers available
  • Branch prediction is perfect, all conditional branches are predicted exactly

Question 126

Question
Perfect caches at The Hardware Model?
Answer
  • All memory accesses take one clock cycle
  • All memory addresses are known exactly
  • All conditional branches are predicted exactly

Question 127

Question
Perfect memory address alias analysis at The Hardware Model?
Answer
  • All memory addresses are known exactly
  • All memory accesses take one clock cycle
  • All conditional branches are predicted exactly

Question 128

Question
Perfect jump prediction at The Hardware Model?
Answer
  • All jumps are perfectly predicted
  • All conditional branches are predicted exactly
  • All memory addresses are known exactly

Question 129

Question
What is Personal mobile device (PMD)?
Answer
  • A collection of wireless devices with multimedia user interfaces
  • A collection of computers with wireless network adapters
  • A collection of Clusters/Warehouse-scale computers

Question 130

Question
Where the embedded microprocessors are used?
Answer
  • In microwaves, washing machines
  • In Personal Computers
  • In mobile phones

Question 131

Question
What functions has Instruction Set Architecture (ISA)?
Answer
  • Serves as the boundary between the software and hardware?
  • Serves as the bridge between CPU and Memory
  • o Serves as the bridge between CPU and Cache

Question 132

Question
What is the TLP?
Answer
  • Time Level Parallelism
  • Technology Level Parallelism
  • Task Level Parallelism

Question 133

Question
By Moore's law, growth rate in transistor count on a chip is doubling?
Answer
  • every 8 to 12 months
  • every 12 to 16 months
  • every 18 to 24 months

Question 134

Question
How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?
Answer
  • 3
  • 2
  • 4

Question 135

Question
What is the “Module reliability” in Dependability?
Answer
  • A measure of the continuous service accomplishment from a reference initial instant
  • a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
  • a measure of the interruption

Question 136

Question
What is response time?
Answer
  • the time between the start and the completion of an event
  • The time to get an information
  • The time spent on execution of a program

Question 137

Question
The guiding principle of reporting performance measurements should be?
Answer
  • reproducibility
  • responsibility
  • creativity

Question 138

Question
What is Temporal Locality?
Answer
  • recently accessed items are likely to be accessed in the near future
  • items whose addresses are near one another tend to be referenced close together in time
  • the nearest data stored in secondary memory

Question 139

Question
What is Spatial Locality?
Answer
  • items whose addresses are near one another tend to be referenced close together in time
  • recently accessed items are likely to be accessed in the near future
  • the nearest data stored in secondary memory

Question 140

Question
What is Amdahl's law?
Answer
  • Defines the speedup that can be gained by using a particular feature
  • Defines time spent on execution of a program
  • Defines data gained in one operation

Question 141

Question
The most popular scheme is set associative, where a set is?
Answer
  • a group of blocks
  • a group of instructions
  • a group of comparatives

Question 142

Question
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
Answer
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the cache cannot contain all the blocks needed during execution of a program
  • If the block placement strategy is not fully associative

Question 143

Question
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
Answer
  • If the cache cannot contain all the blocks needed during execution of a program
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the block placement strategy is not fully associative

Question 144

Question
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
Answer
  • If the block placement strategy is not fully associative
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the cache cannot contain all the blocks needed during execution of a program

Question 145

Question
The “natural” unit of organization of memory:
Answer
  • Word
  • Document
  • Several Computer

Question 146

Question
Main element of cache memory is …
Answer
  • Line
  • Word
  • String

Question 147

Question
Typical levels of Cache memories …
Answer
  • 1,2,3 levels
  • 1,2,3,4,5 levels
  • Cache memories have no levels

Question 148

Question
Select internal memory …
Answer
  • Hard Disk
  • CD-ROM
  • Processor registers

Question 149

Question
Select internal memory
Answer
  • Hard Disk
  • Optical disk
  • Main memory

Question 150

Question
Select internal memory
Answer
  • Cache
  • Magnetic tape
  • Optical disks

Question 151

Question
Select external memory:
Answer
  • Processor registers
  • Cache
  • Main memory
  • Hard disks

Question 152

Question
Select external memory
Answer
  • Optical Disk
  • Cache level 1
  • Registers of processor

Question 153

Question
Select external memory
Answer
  • Magnetic tape
  • Main memory
  • All cache memories

Question 154

Question
Physical types of memories:
Answer
  • Direct, Random
  • Direct, Access time
  • Semiconductor, Optical

Question 155

Question
Physical types of memories:
Answer
  • Semiconductor, Magnetic
  • Word, Block
  • Direct, Random

Question 156

Question
Physical types of memories:
Answer
  • Magneto-optical
  • Number of words
  • Number of bytes

Question 157

Question
Select correct memory hierarchy:
Answer
  • Cache – Main Memory – Secondary storages
  • Secondary storages - Cache – Main Memory
  • Main Memory – Cache - Secondary storages

Question 158

Question
Select correct memory hierarchy:
Answer
  • Processor registers – Cache memory – Main memory
  • Cache memory – Main memory - Processor registers
  • Cache memory – Processor registers - Main memory

Question 159

Question
External, nonvolatile memory is also referred to as …
Answer
  • Auxiliary memory
  • Main memory
  • Levels of cache

Question 160

Question
Types of cache addresses:
Answer
  • Logical, Physical
  • Direct, Associative
  • Set Associative

Question 161

Question
A logical cache stores data using …
Answer
  • virtual addresses
  • virtual addresses and physical addresses
  • Physical addresses

Question 162

Question
The two basic forms of semiconductor random access memory are:
Answer
  • dynamic RAM (DRAM) and static RAM (SRAM)
  • magnetic and optical
  • Winchester and optical disks

Question 163

Question
Main element of cache memory?
Answer
  • Tag
  • Word
  • String

Question 164

Question
A number of chips can be grouped together to form …
Answer
  • a memory bank
  • a memory tags
  • a memory lines

Question 165

Question
Data are recorded on and later retrieved from the disk via a conducting coil named:
Answer
  • The arm
  • The slide
  • The head

Question 166

Question
The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
Answer
  • multiple zoned recording
  • intersector gap
  • the constant angular velocity

Question 167

Question
To increase density, modern hard disk systems use a technique known as:
Answer
  • multiple zone recording
  • the constant angular velocity

Question 168

Question
… can be removed and replaced with another disk.
Answer
  • Processor registers
  • A non-removable disk
  • A removable disk

Question 169

Question
For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
Answer
  • double sided
  • single sided
  • no sides

Question 170

Question
The set of all the tracks in the same relative position on the platter is referred to as …
Answer
  • a cylinder
  • a square
  • a circle

Question 171

Question
On a movable head system, the time it takes to position the head at the track is known as …
Answer
  • transfer time
  • access time
  • seek time

Question 172

Question
The operating system …
Answer
  • is the software that controls the execution of programs on a processor and that manages the processor’s resources.
  • is one which is understandable by us humans
  • is a collection of Clusters/Warehouse-scale computers
  • a program that directly executes instructions written in a programming language

Question 173

Question
The most important functions of the Operating System are:
Answer
  • The scheduling of processes, or tasks
  • Compile C++ program codes
  • Interpret PHP program codes
  • Provide drivers for the remote devices

Question 174

Question
The important function of the Operating System is
Answer
  • Memory management
  • Provide compiler for high level programming languages
  • Increase size of cache

Question 175

Question
How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
Answer
  • Program execution
  • Access to I/O devices
  • Program creation

Question 176

Question
How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
Answer
  • Program creation
  • Access to I/O devices
  • Program execution

Question 177

Question
How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
Answer
  • Access to I/O devices
  • Program execution
  • Program creation

Question 178

Question
How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
Answer
  • Controlled access to files
  • Access to I/O devices
  • System access

Question 179

Question
How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
Answer
  • Error detection and response
  • System access
  • Controlled access to files

Question 180

Question
How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
Answer
  • Accounting
  • System access
  • Controlled access to files

Question 181

Question
Select two independent dimensions of the Operating System:
Answer
  • batch and interactive
  • batch and computer operator
  • Interactive and computer operator

Question 182

Question
Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
Answer
  • Access Permission (AP), Access Permission Extension (APX)
  • Bufferable (B) bit
  • Cacheable (C) bit

Question 183

Question
Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
Answer
  • Bufferable (B) bit
  • Cacheable (C) bit
  • Type Extension (TEX)

Question 184

Question
Different types of parallelism in applications like:
Answer
  • Data-level Parallelism
  • Task-level Parallelism
  • Instruction-level Parallelism
  • All of the above
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