Karteikarten
Processor performance
Karten in diesem Stapel (15)
- 1Name 3 factors which affect processor performanceAny from:
Clock speed
Number of cores
Amount of cache memory
Type of cache memory
Use of pipelining
Word size - 2What is the system clock?An oscillator located on the motherboard
The eventual output (sometimes through Fourier transforms) is a square wave oscillating between 1 and 0
One wave = 1 clock cycle
Clock speed = frequency of wave (measured in Hz) - 3System clock and CPU speedAll processor activities start when the clock changes from either 0 to 1 or 1 to 0
If an instruction is finished, it must wait for this to occur before the next can commence
Faster clock speed means more clock cycles and faster instruction completion - 4Typical modern clock speeds2-4GHz
- 5CPU coresAn example Von-Neumann processor has one of each CPU component - this is a single-core processor
Many modern CPUs have multiple cores within one integrated circuit
Each core is a separate processor with its own components
Cores are theoretically able to process one instruction each simultaneously
Doubling cores does not double the performance - cores have to communicate and programs must be written in parallel to take advantage of multiple cores.
Diminishing returns for additional cores as extra heat increases Mean Time to Fail - 6CacheA small amount of very fast and expensive memory which is physically on the CPU
When an instruction is fetched from memory, it is copied to the cache in case it is needed soon after - this is faster than going back to main memory
As the cache fills up, unused instructions or data will be deleted to make room for newer instructions/data - 7Levels of cacheL1: Extremely fast, but small (2-64KiB)
L2: Fairly fast, medium-sized (256KiB-2MiB)
L3: Not always present, larger still and slow - 8PipeliningFDR cycle is normally implemented sequentially, leaving much of the processor idle
Pipelining makes full use of the processor by applying each stage of the FDR cycle to different programs
Completed sections are held in a buffer near the CPU until the next stage can be performed - 9Types of pipeliningPipelining is sometimes divided into an instruction pipeline and an arithmetic pipeline
Instruction pipeline represents stages of FDR cycle that can be performed
Arithmetic pipeline represents stages of an arithmetic operation that can be decomposed and overlapped - 10Problems with pipeliningRequires the program to be predicted - if something unexpected happens, the CPU has to empty the buffer - known as 'flushing the pipe' - and start again
Flushing the pipe too often can reduce CPU performance - 11Structure of RAMSingle-bit units are often held in a \(nxn\) matrix
RAM consists of a number of these matrices - 12Definition of word in memoryA group of bits in memory with its own specific address
Each bit is situated on its own matrix, at the same address - 13Effect of address bus on wordsThe address bus carries the address of the word from the CPU to RAM.
The number of addresses - and hence the number of words - is limited by the size of the address bus
Size of a matrix unit in RAM is limited by address bus width - 14Effect of data bus on wordsData bus transmits data held in a word of memory
Size of data bus = maximum word size
= maximum number of chips on RAM
= number of matrix units in RAM - 15Machine code and word sizeStructure of machine code places regulations on the relative sizes of the address and data buses
Data bus must be larger than address bus because it has to carry instructions containing an opcode and an address
Difference between address and data bus widths determines maximum instruction set size
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- A level OCR A level Computer Science (Topic 1 - Components of a Computer) Karteikarten am Processor performance, erstellt von James Norman am 05/03/2019.
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