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  1. 1T/F: The control unit fetches the next instruction from memory using the contents of the ROM to determine the address of the instruction in memory.False
  2. 2T/F: The ALU of a computer will interpret and execute programs, and it has a control unit.False
  3. 3T/F: In computer level hierarchy, the level 2 machine level is also known as the assembly language level.False
  4. 4T/F: 6 bytes is 32 bits.False
  5. 5T/F: The JK flip flop is the fundamental circuit of computer memory.False
  6. 6T/F: The complement of A+B is A'B'.False
  7. 7T/F: XOR stands for 'NOT OR' gate.False
  8. 8T/F: Maskable interrupts are low-priority interrupts that can be ignored.True
  9. 9T/F: The binary number of the decimal number 39 is 100101.False
  10. 10T/F: The Boolean function F(x,y) = xy' + xy can be simplified to x.True
  11. 11T/F: The Boolean function F(A, B, C) = (AB)' +A'C' is equivalent to A'.False
  12. 12T/F: Clock cycle time is the reciprocal of clock frequency.True
  13. 13T/F: Parallel processing allows a computer to simultaneously work on subparts of a problem.True
  14. 14T/F: The next state of a sequential circuit will be determined only by its inputs.False
  15. 15T/F:In computer architecture, the I/O operation is the least efficient operation.True
  16. 16T/F: Design of a sequential circuit cannot start with Deterministic Finite Automata.False
  17. 17T/F: xx' will be 1.False
  18. 18T/F: One way of improving CPU throughput is reduction in the number of cycles per instruction.True
  19. 19Given the following code paragraph, which is the corresponding instruction in Marie? MBR <- PC MAR <- X M[MAR] <- MBR MBR <- X AC <- 1 AC <- AC + MBR PC <-AC a JumpI X b. JnS X c. AddI X d. None of themb. JnS X
  20. 20Convert the following unsigned base 10 number to base 2: 37(10) = _______________________(2) a. 1001000 b. 101100 c. 100101 d. 1100110c. 100101
  21. 21The complement of (AB) + C is: a. A' + B' + C' b. A'B' + C' c. A'C' + B'C' d. A' + B' + Cc. A'C' + B'C'
  22. 22Which of the following events can cause an interrupt in a computer? a. An user break is issued b. An I/O request by the user or program c. A critical error d. All of themd. All of them
  23. 23In SR flip-flop, if the current state is 1, and when S=R=1, the next state of the flip-flop will be . a. 0 b. 1 c. 2 d. undefinedd. undefined
  24. 24The Boolean expression for F is: a. xz' + x'y' + yz b. x'z + xy + y'z' c. xyz d. (x+z)(x'+y')(y+z)a. xz' + x'y' + yz
  25. 25An 400 MHZ clock has a cycle time of: . a. 1.25ns b. 2.5ns c. 4ns d. 0.4nsb. 2.5ns
  26. 26For a 4M word-addressable memory, how many address lines are at least needed? a. 21 b. 22 c. 20 d. 12b. 22
  27. 27In MARIE system, how many signals in total do we need to define for reading memory and registers? a. 3 b. 4 c. 5 d. 6a. 3
  28. 28What is the corresponding hex content of the instruction Jump 105 in Marie? a. 3105 b. 6106 c d. None of themc. 9105
  29. 29When creating a Kmap, which of these is not a rule for creating a minterm group? a. Groups must be a size of a power of 2 b. Groups must be as large as possible. c. Groups may never contain a zero. d. Groups may never overlap.d. Groups may never overlap.
  30. 30Given the following code paragraph, which is the corresponding instruction in Marie? MAR <- X MBR <- M[MAR] MAR <- MBR MBR <- AC M[MAR] <- MBR a. Load X b. Loadl X c. Store X d. Storel Xd. Storel X
  31. 31Complete the characteristic table for the sequential circuit shown below a. Next State A - Row#: 1 = 0; 2 = 1; 3 = 1; 4 = 0 b. Next State A - Row#: 1 = 1; 2 = 0; 3 = 1; 4 = 0 c. Next State A - Row#: 1 = 1; 2 = 0; 3 = 0; 4 = 1 d. Next State A - Row#: 1 = 0; 2 = 0; 3 = 1; 4 = 1d. Next State A -
    Row#: 1 = 0; 2 = 0; 3 = 1; 4 = 1    Complete the characteristic table for the sequential circuit shown below a. Next State A - Row#: 1 = 0; 2 = 1; 3 = 1; 4 = 0 b. Next State...
  32. 32Suppose we have a 128-word memory that is 8-way low-order interleaved, which of the following statements is true? a. It uses 7 memory banks b. we use the low-order 3 bits to identify the memory bank c. We need 6 bits for each address d. none of themb. we use the low-order 3 bits to identify the memory bank
  33. 33Which of the following statements is a typical instruction of a three-address ISA? a. Load R1, X b. Store Temp c. Mult R1, X, Y d. none of themc. Mult R1, X, Y
  34. 34Given an infix expression (a + b) - c * d, which of the following options is the corresponding postfix expression? a. a + b * cd- b. ab+*cd- c. ab+cd*- d. none of themc. ab+cd*-
  35. 35Given the memory, register R1, and an instruction as follows, after the execution of the instruction, what is the value in AC by using indexed addressing? a. 0x500 b. 0x600 c. 0x700 d. none of themc. 0x700
  36. 36Given the following instruction pipelining diagram, and assume each cycle time is T, what is the total time needed to finish the 2 instructions? a. 6T b. 7T c. 8T d. none of themb. 7T
  37. 37—
  38. 38Assume a byte-addressable memory consisting of 16 bytes into 8 blocks. Cache contains 4 blocks. How many binary bits are needed to identify all the cache blocks? a. 1 b. 2 c. 4 d. none of themb. 2

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Karteikarten am Ohne Titel, erstellt von Alexandria Banta am 08/12/2018.
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