Mindmap
Microprocessors
Inhalt der Mindmap
Microprocessors
Numbers
Characters, floats, ends, memory
- IEE 754
- Byte ordering
- Big endian
- Little endian
- Memory
- SRAM
- DRAM
- Latencies
- DDR
- ECC memory
- Hamming code
Processor architecture
- Busses
- Speed
- Determined by
- Frequency
- Width
- Latency
- Determined by
- Constraints
- North & south bridges
- North bridge
- CPU
- Front side
- Back side
- Cache
- RAM
- Graphics
- CPU
- South bridge
- Disk
- PCI slots
- Ethernet
- North bridge
- HyperTransport
- Memory bus
- System bus
- Graphics bus
- Multiprocessor
- Disk connections
- External bus
- Speed
- I/O
- Port mapped
- Memory mapped
- I/O mechanisms
- Polling
- Interrupts
- DMA
- Execution
- Fetch-Execute instruction cycle
- Instruction set architectures
- RISC
- CISC
- Instruction set architectures
- Increase performance
- Clock frequency
- Pipelines
- Stalls
- Hazards
- Data
- Stall
- Forwarding
- Control
- Stall
- Branch prediction
- Structural
- Data
- Hazards
- Stalls
- Cache
- Fetch-Execute instruction cycle
- Registers
- ALU
- FPU
- Cache
- Hit
- Miss
- Handling misses
- CPU time calculations
- Associativity
- Fully associative
- Direct mapped
- Set associative
- Cache coherency
- Vector units
- Busses
Pentium processors
- Superscalar execution
- Register renaming
- Branch prediction
- Floating point ALU
- Trends
- P6 microarchitecture
- P6 pipeline
- Out of order execution
- Instruction lifecycle
- Reordering
- Pentium 4
- Trace cache
- Backend
- Decoding x86
Low power multicore architectures
- Moore's law
- Trend
- Multithreading
- Hyperthreading
- Multicore approaches
- Small number of 'big' cores
- Core 2 Duo
- Core i7 Nehalem
- Core i7 3960 Sandy Bridge
- Large number of 'small' cores
- Asymmetric
- Small number of 'big' cores
- Cell processor
- Graphics card
- Steaming processor
- Vector processor
Informationen
- Beschreibung
- Mindmap am Microprocessors, erstellt von Ken Reycruz am 18/05/2015.
- Erstellt von
- Ken Reycruz
- Aufrufe
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