Mindmap
Lecture 12 - Serial Peripheral Interface (2)
Inhalt der Mindmap
Lecture 12 - Serial Peripheral Interface (2)
SPI on MBED
- SPISlave
- format
- frequency
- receive
- read
- reply
I/O Port Expansion
- The MBED has 26 general purpose I/O lines (p5-p30)
- Many I/O lines have multiple roles
- Not all I/O lines are available
- Extra I/O resources are sometimes required
- e.g. where a large number of indicators are required
- e.g. external memory, accelerometer, temperature sensors...
- The MBED incorporates an SPI for this type of I/O expansion
Use of SPI to Realise Extra 8-bit Output Port
- Extra 8-Bit Parallel Output Port
- The 74HC595 is an 8-bit serial load register with output latch, outputs remain unaffected while new data is shifted in
- Data shifted in by ShiftCLK, O/P updated by LatchClock
- Transfer to 74HC595 O/P register is achieved by writing to SPIBUF then pulsing LatchClock
- HC595 inputs on +VE clock edge
- Therefore SPI Port set up to Output on -VE clock edge
- Extra 8-Bit Parallel Output Port
Use of SPI to Realise Extra 16-Bit Output Port
- In this case two 74HC595s are wired as a 16-bit shift register
- Can be used as 16-bit O/P port or two 8-bit ports
- This approach can be extended
Reading Input Port
- Data shifts on +VE edge of SCK
- Data Sampled by MISO on -VE edge of SCK so data is stable when sampled
- To read I/P Port:
- Load 74HC165, by pulsing LOAD
- Clear SPIIF
- Write dummy data to SPI port to start shifting process
- Wait for SPIIF to go high (Data shift complete)
- Read SPI Port
- Wait for SPIIF to go high (Data shift complete)
- Write dummy data to SPI port to start shifting process
- Clear SPIIF
- Load 74HC165, by pulsing LOAD
- Data shifts on +VE edge of SCK
Interfacing to Several Devices using SPI
- SPI Pins connect to all devices
- Separate CS Lines
- P10 selects EEPROM
- P11 selects RTC
- P12 selects RS232 interface chip
SPI Assessment
- The electronic hardware is simple, data can be transferred rapidly
- Negatives:
- Each Slave requires its own CS Line
- Expensive in pinout for large system
- There is no acknowledgement from the receiver
- Three is no error-checking
- Overall SPI is simple, convenient and low-cost, but not suitable for complex/high reliability systems
- Each Slave requires its own CS Line
Informationen
- Beschreibung
- Degree EL560 (Microcontroller Engineering) Mindmap am Lecture 12 - Serial Peripheral Interface (2), erstellt von Tom Revise am 03/01/2021.
- Erstellt von
- Tom Revise
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