Chapter 7 :Pipelining & RISC

Chapter 7 :Pipelining & RISC

1. Instruction Execution Characteristics

   • High-level languages (HLLs)
   • Semantic gap
   • Operations performed
   • Operands used
   • Execution sequencing

2. Control Hazard

   • known as a branch hazard
   • Occurs when the pipeline makes the wrong decision on a branch prediction
   • Brings instructions into the pipeline that must subsequently be discarded

3. Pipeline Hazards

   • Resource
   • Data
   • Control

4. Pipelining of Unequal Stages

   • largest of the stage delay to be the cycle time
   • No stage overlaps & latency must be constant
   • instruction overlap is the same as the cycle time

5. Additional Stages

   • Fetch instruction (FI)
   • Decode instruction (DI)
   • Calculate operands (CO)
   • Fetch operands (FO)
   • Execute instruction (EI)
   • Write operand (WO)

6. Pipelining

   • allows the execution of multiple instructions to overlap in time
   • new data/instruction is processed by a stage potentially as soon as it is done

7. Use of a Large Register File

   • Requires compiler to allocate registers
   • Allocates based on most used variables in a given time
   • Requires sophisticated program analysis
   • More registers
   • more variables will be in registers

8. Implications

   • HLLs can best be supported by optimizing performance of the most time-consuming features of typical HLL programs
   • Three elements characterize RISC architectures:
     • Use a large number of registers or use a compiler to optimize register usage
     • Careful attention needs to be paid to the design of instruction pipelines
     • Instructions should have predictable costs and be consistent with a high-performance implementation

9. Types of Data Hazard

   • Read after write (RAW), or true dependency
   • Write after read (WAR), or antidependency
   • Write after write (WAW), or output dependency

10. CISC

    • There is a trend to richer instruction sets which include a larger and more complex number of instructions
    • Two principal reasons for this trend
      • A desire to simplify compilers
      • A desire to improve performance
    • two advantages to smaller programs
      • The program takes up less memory
      • Should improve performance

11. Characteristics of Reduced Instruction Set Architectures

    • One machine instruction per machine cycle
    • Register-to-register operations
    • Simple addressing modes
    • Simple instruction formats

12. RISC versus CISC Controversy

    • Quantitative
    • Qualitative
    • Problems with comparisons