HLS

Seite 1

Introduction to HLS

A behavioural description (i.e., functional specifications) is used as the starting point for HLS. It specifies the behaviour in terms of operations, assignment statements, and control constructs in a Hardware Description Language.

Seite 2

Introduction to HLS

A behavioural description (i.e., functional specifications) is used as the starting point for HLS. It specifies the behaviour in terms of operations, assignment statements, and control constructs in a Hardware Description Language (HDL)

The first step in HLS is compilation of the HDL and transformation into an internal representation. Most HLS techniques use Control and Data Flow Graph (CDFG) as the representation, because it contains both the data flow and the control flow.

The second step of the HLS, which plays a key role in transforming a CDFG (i.e., behavioral) representation into a RTL (i.e., structural) representation, is operation-scheduling (called just “scheduling” in HLS terminology). Scheduling involves assigning operations of the CDFG to so-called control steps. A control step usually corresponds to a cycle of the system clock, the basic time unit of a synchronous digital system.

The third step is Allocation, which chooses functional units and storage elements from the design library. The design library has several alternatives for a given functional unit or a storage unit. For example, for a functional unit like adder, there can be many options like ripple-carry adder, carry-look-ahead-adder etc. Similarly, for storage elements there can be different types of registers like registers with only resets, registers with both pre-sets and resets, registers with pre-sets, resets and load [4] etc. Among the alternatives, the allocation algorithm must select the one that matches the design constraints best and maximizes the optimization objective.