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Fragen in diesem Quiz (60)
11. What is not a main structural element of a computer system?
- AMain Memory
- BI/O Modules
- CSystem Bus
- DOperating system
- EProcessor
22. Which of the following registers are used by the processor to exchange data with memory?
- AI/OAR and I/OBR
- BProgram status word
- CPC and IR
- DMAR and MBR
3
3. Which of the following registers are used by the processor to exchange data with input/output module?
- AI/OAR and I/OBR
- BMAR and MBR
- CProgram status word
- DPC and IR
4
4. Which of the following element of a computer system controls the operation of the computer and performs its data processing functions?- A4. Which of the following element of a computer system controls the operation of the computer and performs its data processing functions?
- BProcessor
- CSystem bus
- DI/O modules
- EMain memory
55. Which of the following element of a computer system stores data and programs?
- AI/O modules
- BProcessor
- CSystem bus
- DMain memory
66. Which of the following provides for communication among elements of a computer system?
- A• I/O modules
- B• Processor
- C• System bus
- D• Main memory
77. Which of the following element of a computer system moves data between the computer and its external environment?
- A• Main memory
- B• Processor
- C• I/O modules
- D• System bus
88. The processor contains a single data register, called
- A• PSW
- B• AC
- C• IR
- D• PC
99. This register specifies a particular input/output device
- A• I/OBR
- B• Memory buffer register
- C• I/OAR
- D• Memory address register
1010. This register is used for the exchange of data between an I/O module and the processor
- A• I/OBR
- B• Memory buffer register
- C• I/OAR
- D• Memory address register
11
11. This register contains the data to be written into memory or which receives the data read from memory- A• I/OBR
- B• memory address register
- C• memory buffer register
- D• I/OAR
1212. This register specifies the location in memory for the next read or write
- A• I/OBR
- B• Memory buffer register
- C• I/OAR
- D• Memory address register
1314. Which register contains the address of the next instruction to be fetched?
- A• process counter
- B• program counter
- C• execution register
- D• instruction register
1414. Which register contains the instruction most recently fetched?
- A• process counter
- B• instruction register
- C• execution register
- D• program counter
1515. Which register contains condition codes set by the processor hardware as the result of operations?
- A• Stack pointer
- B• Program status word
- C• Accumulator
- D• Program counter
16
16. The fetched instruction is loaded into the- A• PC
- B• Memory
- C• Accumulator
- D• IR
1717. At the beginning of each instruction cycle, the processor fetches an instruction from the memory. The address of the instruction is held in
- A• PC
- B• MAR
- C• MBR
- D• IR
1818. The processor is executing ‘Load AC from memory’ instruction. Choose the correct micro-instructions:
- A• PC -> MAR
M -> MBR
MBR -> AC
IR -> MAR
M -> MBR
MBR -> AC - B• PC -> MBR
M -> MAR
MAR -> IR
IR -> MAR
M -> MBR
MBR -> AC - CPC -> MAR
M -> MBR
MBR -> IR
IR -> MAR
M -> MBR
MBR -> AC - D• PC -> MAR
M -> MBR
MBR -> IR
IR -> MBR
M -> MAR
MAR -> AC
- A• PC -> MAR
1919. When an I/O device completes an I/O operation, the device issues an interrupt signal to the processor and then:
- A• The processor stops execution of the current instruction without finishing it and responds to the interrupt
- B• The processor loads the program counter with the entry location of the interrupt-handling routine
- C• The processor saves information needed to resume the current program at the point if interrupt
- D• The processor finishes execution of the current instruction before responding to the interrupt
2020. When the time required for the I/O operation is less that the time to complete the execution of instructions between write operations in the user program, it is:
- A• Short I/O wait
- B• Long I/O wait
- C• Slow I/O wait
- D• Fast I/O wait
2121. When the time required for the I/O operation will take much more time than executing a sequence of user instructions, it is:
- A• Short I/O wait
- B• Fast I/O wait
- C• Long I/O wait
- D• Slow I/O wait
2222. If there no interrupts, after each write operation, the processor must:
- A• Pause and remain idle until the I/O operation
- B• Save the PSW and PC onto control stack
- C• Finish execution of current instruction
- D• Load new PC value
2323. Complete the relationship concerning the memory systems: faster access time –
- A• smaller cost per bit
- B• faster access speed
- C• greater cost per bit
- D• lower capacity
2424. Complete the relationship concerning the memory systems: greater capacity –
- A• smaller cost per bit
- B• faster access speed
- C• greater cost per bit
- D• lower capacity
2525. Complete the relationship concerning the memory systems: greater capacity –
- A• faster access speed
- B• greater cost per bit
- C• slower access time
- D• lower capacity
2626. The smaller, more expensive, faster memory is:
- A• Register
- B• Main memory
- C• Cache
- D• Disk drive
2727. If the accessed word is found in the faster memory, that is defined as a:
- A• evrika
- B• hit
- C• win
- D• bingo
2828. If the accessed word is not found in the faster memory, that is defined as a:
- A• Loss
- B• zero
- C• miss
- D• ricochet
2929. This type of memory is nonvolatile:
- A• Main memory
- B• Cache
- C• Secondary memory
- D• Register
3030. When a processor attempts to read a byte or word of memory, it firstly checks the:
- A• Main memory
- B• Secondary memory
- C• Cache
- D• Register
3131. This chooses which block to replace when a new block is to be loaded into the cache and the cache already had all slots filled with other blocks:
- A• locality of reference
- B• cache size
- C• write policy
- D• replacement algorithm
3232. If the contents of a block in the cache are altered, then it is needed to save it back to main memory before replacing it. This is called:
- A• replacement algorithm
- B• locality of reference
- C• mapping function
- D• write policy
3333. Which of the following is not a technique possible for I/O operations?
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3434. The processor issues an I/O command to a module and waits, periodically checking the status of the I/O module until it finds that the operation is complete.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3535. The I/O module performs the requested action and then sets the appropriate bits in the I/O status register but takes no further action to alert the processor.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3636. The main disadvantage of this technique: it is a time-consuming process that keeps the processor busy needlessly.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3737. The processor issues an I/O command to a module and then go on to some other useful work.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3838. The I/O module performs the requested action and alerts the processor to request service when it is ready to exchange data with the processor.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
3939. The main disadvantage of this technique: consumes a lot of processor time, because every word of data that goes from memory to I/O module or from I/O module to memory must pass through the processor.
- A• Programmed I/O
- B• Interrupt-driven I/O
- C• Manual memory access
- D• Direct memory access (DMA)
4040. The processor issues an I/O command to a separate module, by sending the type of operation (read/write), the address of the I/O device, the starting location in memory for data, number of words. Then the processor continues with other work.
- A• Direct memory access (DMA)
- B• Manual memory access
- C• Programmed I/O
- D• Interrupt-driven I/O
4141. The module transfers the entire block of data to/from memory without going through the processor.
- A• Direct memory access (DMA)
- B• Manual memory access
- C• Programmed I/O
- D• Interrupt-driven I/O
4242. The main disadvantage of this technique: there is a competition for bus usage.
- A• Direct memory access (DMA)
- B• Manual memory access
- C• Programmed I/O
- D• Interrupt-driven I/O
4343. A hardcopy sign-up sheet was used to reserve computer time with
- A• Time allocating
- B• Time slicing
- C• Time sliding
- D• Time scheduling
4444. A system clock generates interrupts at a rate of approximately one every 0.2 seconds. At each clock interrupt, the OS regained control and could assign the processor to another user. This technique is known as
- A• Time allocating
- B• Time slicing
- C• Time sliding
- D• Time scheduling
4545. Batch operating systems were used (years)
- A• In early 1960s
- B• From the mid-1950 to early 1960s
- C• From the late 1940s to the mid-1950s
4646. Job control language was used
- A• From the mid-1950s to early 1960s
- B• From late 1940s to the mid-1950s
- C• used to provide instructions to the monitor,In early 1960s
4747. Serial processing was used
- A• From the mid-1950s to early 1960s
- B• From late 1940s to the mid-1950s
- C• In early 1960s
4848. The central idea in this system was the use of a piece of software known as the monitor
- A• Serial processing
- B• Multiprogrammed batch system
- C• Simple batch system
- D• Time-sharing-system
4949. The concept of a batch operating system was developed to
- A• Minimize processor utilization
- B• Support interactive mode
- C• Minimize response time
- D• Maximize processor utilization (To improve utilization)
5050. The concept of modes of operation (user mode, system mode) was introduced with
- A• Serial processing
- B• Multiprogrammed batch system
- C• Simple batch system
- D• Time-sharing-system
5151. The principal objective of the time-sharing system is to
- A• Maximize processor utilization
- B• Maximize response time
- C• Minimize processor utilization
- D• Minimize response time
5252. The processor was often idle waiting for the I/O instruction to conclude. To overcome the problem the following approach was introduced: when one job needs to wait for I/O, the processor can switch to the other job. This was a
- A• Time-sharing-system
- B• Serial processing
- C• Simple batch system
- D• Multiprogramming or multitasking batch system
5353. The programmer interacted directly with the computer hardware with
- A• Multiprogrammed batch systems
- B• Time-sharing-systems
- C• Serial processing
- D• Simple batch systems
5454. The serial processing presented two main problems:
- A• scheduling
- B• multiprogramming
- C• time slicing
- D• using a monitor
- E• setup time
5555. There were no OS with
- A• Multiprogrammed batch systems
- B• Time-sharing-systems
- C• Serial processing
- D• Simple batch systems
5656. This system handles multiple interactive jobs
- A• Multiprogrammed batch system
- B• Serial processing
- C• Simple batch system
- D• Time-sharing-system
5757. This system was developed by General Motors for the use on an IBM 701
- A• Time-sharing system
- B• Multiprogrammed batch system
- C• Serial processing
- D• Simple Batch Systems or GM-NAA I/O
5858 This type of system was developed at MIT by a group known as Project MAC for the IBM 709 in 1961
- A• Time-sharing-system
- B• Simple batch system
- C• Multiprogrammed batch system
- D• Serial processing
5959. Lost signals, duplicate signals received'. This is
- A• Failed mutual exclusion
- B• Deadlocks
- C• Nondeterminate program operation
- D• Improper synchronization
6060. 'Two or more programs hung up waiting for each other'. This is
- A• Improper synchronization
- B• Nondeterminate program operation
- C• Deadlocks
- D• Falled mutual exclusions
Informationen
- Beschreibung
- YUNIKOVA
- Autor
- Axakalov Beksultan
- Sprache
- English
- Aufrufe
- 5
- Schlagwörter
- Bewertung
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