Quiz
[CPSC313 Final] Unit 1 Sequential CPU
Dieses Quiz enthält Fragetypen, die sich im gewohnten Player öffnen.
Fragen in diesem Quiz (32)
1Y86 Memory is Little Endian
- ARichtig
- BFalsch
2The Little Endian version of 0x80081355 (boobless) is 0x[blank_start]55130880[blank_end]
- A55130880
3The stages in the sequential CPU are executed as follows and in this order (usually): [blank_start]fetch[blank_end], [blank_start]decode[blank_end], [blank_start]execute[blank_end], [blank_start]memory[blank_end], [blank_start]write back[blank_end], [blank_start]update PC[blank_end].
- Afetch
- Bdecode
- Cexecute
- Dmemory
- Ewrite back
- Fupdate PC
4Fetch is responsible for which actions? Check all that apply.
- AUse pc to read next instruction from memory into instruction register
- BDetermine instruction length and extract pieces of instruction
- CAdvance the pc to the address of next instruction in sequence
- DRead values from register file
- EUpdate the pc for taken jump instructions
5Which of the following is a decode action?
- Aread values from register
- Bdetermine instruction length and extract pieces of instruction
- Caccess main memory
- Ddecode the difficulty of this course into a binary representation of tears and not tears
6Which of the following is an execute stage action?
- Aperform ALU operations and determine whether jumps are taken
- Bset the pc for taken jumps
- Caccess main memory
- Dcry profusely into a bowl of alphabits hoping they'll arrange themselves into the proper values for the next stage
7Which of the following is a memory stage action?
- Aaccess main memory, duhhhhhhhhhh
- Baccess main memory and write the values back to the register file, duhhhhhhhhhhh
- Cwhen in doubt choose c
- Dadvance the pc to the next memory address in the sequence
8Which of the following is a write back stage action?
- Awrite values back to register file
- Bwrite values back to main memory
- Cwrite values back to the pc
- Dforge your computer science degree when failing this course leads you into months of crippling depression
9Which of the following is an update pc stage action?
- Aupdate the pc for taken jump instructions
- Buse pc to read next instruction from memory into instruction register
- Cadvance the pc to the address of the next instruction sequence
- DThe Obviously Correct Answer
10In a simplified assembly-line flow of execution this is what would happen: [blank_start]get instruction from memory[blank_end], [blank_start]read registers[blank_end], [blank_start]do math[blank_end], [blank_start]read or write data from/to memory[blank_end], [blank_start]write registers[blank_end]
- Awrite registers
- Bread or write data from/to memory
- Cdo math
- Dread registers
- Eget instruction from memory
11You like these drag-and-drop questions don't you?
- ARichtig
- BFalsch
12We can have math instructions that read from memory (Example: addl (%ebx), (%ebx) )
- ARichtig
- BFalsch
13Can we have an instruction that copies from one memory location to another?
- AOh for sure, honey.
- BNo, no we can not.
- CI need another drink.
14Check all the special purpose registers of the Fetch stage in a Sequential CPU
- Aicode - opcode of current instruction
- Bifun - function code
- CrA/rB - reg numbers
- DvalC - constant, offset, or jump target
- EvalP - address of next instruction in sequence
- FvalM - value read to main memory
- GdstE - destination for when instruction reaches execute
- HnewPC - address of next jump
- Ibch/cnd - satisfied condition for branching
15Check all the special purpose registers of the Decode stage in a Sequential CPU
- AsrcA - often rA
- BsrcB - often rB
- CdstE - the destination for valE
- DdstM - the destination for valM
- EvalA - val of reg number srcA (i.e. r[srcA])
- FvalB - val of reg number srcB (i.e. r[srcB])
- GvalE - the value from E
- HvalM - the value from M
16Check all the special purpose registers of the Execute stage
- AvalE - computed by ALU
- Bbch/cnd - satisfaction of branch condition
- CvalM - value to write to memory
- DdstE - destination for valE
- EdstM - destination for valM
- FsrcA - register number to read
17Check all the special purpose registers of the Write Back stage in a Sequential CPU
- AdstE - reg number to store valE
- BdstM - reg number to store valM
- CvalM - value read from main memory
- DvalC - constant to detect jump condition for PC update
- EnewPC - address of next instruction to execute
18Check all the special purpose registers of the PC Update stage in a sequential CPU
- AnewPC - address of next instruction to execute (taking jxx, call, and ret into account)
- BvalC - jump target
- Cyour performance on this exam could potentially cost you hundreds of dollars and maybe even keep you in school long enough for all the jobs to be gone
19Which of these bastards is most appropriate as a Register Transfer Language syntax for the variable f.icode:f.iFun?
- A<= M1[PC] - Meaning 1 byte from the memory address held in the PC
- B<=M1[PC] - Meaning 1 bit from the memory address held in the PC
- C<=M1[PC] - Meaning 1 hex digit from the memory address held in the PC
- DWhat is a byte?
- EWhat is a bit?
- FHow many bits are in a byte?
- GHow many hex digits make up a byte?
- H<= M4[PC] - Meaning 1 byte from the memory address held in the PC
- I<= M4[PC] - Meaning 4 bits from the memory address held in the PC
- J<= M4[PC] - Meaning 2 hex digits from the memory address held in the PC
20Alright then. You think you so damn special. Let's see if you get this one. Consider the following:
f.icode:f.iFun <= M1[PC]
f.rA:f.rB <= M1[PC+1]
f.valC <=M4[PC+2]
f.valP <= PC + [blank_start]6[blank_end]- A6
21This course is painful
- ARichtig
- BFalsch
22Which of the following best describes the Decode stage?
- AIt reads values from the register file.
- BIt determines what the instruction will do and divides it into its constituent parts.
- CIt reads and writes values from and to the register file.
- DIt determines which register numbers (if any) will be read and written and then reads values from the register file.
23Which of the following best describes the Execute stage?
- AIt performs all mathematical (and logical) operations required by the instruction (excluding updating the PC)?
- BIt performs some of the mathematical (and logical) operations required by the instruction (excluding updating the PC).
- CIt performs all operations required by the instruction.
- DIt performs all operations required by the instruction except accessing memory and storing results.
24Which of the following best describes the Fetch stage?
- AIt gets all of the data needed to execute the instruction from memory.
- BIt gets the instruction from memory and places it in a register.
- CIt gets the instruction from the register file.
- DIt gets the instruction from memory and register values from the register file.
25Which of the following best describes the Writeback stage?
- AIt writes results into memory.
- BIt writes results into either memory or the register file as required by the instruction
- CIt determines what values should be written to the register file and where they should be written.
- DIt writes results into the register file.
26Which of the following best describes the Memory stage?
- AIt performs all memory reads required by the instruction (except reading the instruction itself).
- BIt performs all access to memory required by the instruction (except reading the instruction itself).
- CIt performs all memory writes required by the instruction.
- DIt performs all access to memory required by the instruction (including reading the instruction itself).
27Which of the following is true about the classic, 5-stage RISC pipeline we discussed in class?
- AThe memory stage must precede the execute stage so that all operand values are available before arithmetic operations (e.g., add, subtract etc) are performed on them.
- BThe execute stage must precede the memory stage so that memory addresses can be calculated before memory is accessed.
- CThe ordering of execute and memory stages does not really matter.
28Which of the following is true about the classic, 5-stage RISC pipeline we discussed in class?
- AMemory is accessed in only one stage (except for reading the instruction itself).
- BMemory is accessed in more than one stage (except for reading the instruction itself).
29Which of the following is true about the classic, 5-stage RISC pipeline we discussed in class?
- AThe register file is accessed in only one stage.
- BThe register file is accessed in more than one stage.
30True or False, The following instruction could be implemented in the classic, 5-stage pipeline we discussed in class (ie., without adding or reording stages).
* move an immediate value (i.e., a constant stored in the instruction) into memory.- ARichtig
- BFalsch
31True or False, The following instruction could be implemented in the classic, 5-stage pipeline we discussed in class (ie., without adding or reording stages).
* add a value from memory to a value in a register and store the result in a register- ARichtig
- BFalsch
32True or False, The following instruction could be implemented in the classic, 5-stage pipeline we discussed in class (ie., without adding or reording stages).
* swap a value in a register with a value in memory- ARichtig
- BFalsch
Informationen
- Beschreibung
- This is for UBC's 313 course unit 1 for studying for the final.
- Autor
- Zim Brightwood
- Sprache
- English
- Aufrufe
- 0
- Schlagwörter
- Bewertung
- Noch keine Bewertungen Bewerte dieses Quiz