Quiz
[Final Study] Unit 2 Pipelined CPU
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Questions in this quiz (49)
1Throughput is
- Athe rate at which instructions leave the pipeline
- Btotal time it takes an instruction to be processed by a stage
- Cthe rate at which instructions move to the next register
- Dtotal time it takes an instruction to be processed by the entire pipeline
2Latency is
- Atotal time it takes an instruction to be processed by the entire pipeline
- Bthe rate at which instructions leave the pipeline
- Cthe rate at which instructions move to the next register
- Dtotal time it takes an instruction to be processed by a stage
3Pretend the pipeline is a cafeteria line in prison. Who is throughput and who is latency?
- AThroughput is the security guard concerned with how often people are leaving the line so nobody shanks anybody. Latency is BUBBA watching Skinny Pete make his way through the line so he can shank him after he gets his food.
- BThroughput is the warden watching the prisoners out in the field and latency is the secretary having an affair with the gardener *gasp*~
- CThroughput is the rate at which the soap leaves a prisoners hand in the showers and latency is the total time it takes to pick it up
4Pipeline registers are placed [blank_start]between each stage[blank_end], those registers store [blank_start]inputs for that stage[blank_end], each stage executes [blank_start]in parallel[blank_end] working on a different instruction
- Abetween each stage
- Bafter each stage
- Cbefore each stage
- Dinputs for that stage
- Eoutputs for that stage
- Finputs for the next stage
- Gin parallel
- Hsequentially
5And instruction is [blank_start]in flight[blank_end] when it is currently being executed by the pipeline. Once the instruction completes the pipeline, it is [blank_start]retired[blank_end].
- Ain flight
- Bexecuting
- Clatent
- Dactive
- Eretired
- Ffinished
- Gcomplete
- Hready
6The pipeline instructions are executed in order
- ATrue
- BFalse
7Instruction-level parallelism exists between a pair of instructions if
- Atheir execution order does not matter
- Btheir execution order matters
8The pipeline requires some parallelism
- ATrue
- BFalse
9Dependencies exist if execution order doesn't matter
- ATrue
- BFalse
10Consider the variables a and b. A causal dependency is defined as A<B (Instruction A immediately precedes B) if
- AB reads value written by A
Example:
a = 1;
b = a; - BB write to visible location written by A
Example:
a = 1;
a = 2; - CB write to a location read by A
Example:
b = a;
a = 1;
- AB reads value written by A
11Consider the variables a and b. An output dependency is defined as A<B (Instruction A immediately precedes B) if
- AB write to visible location written by A
Example:
a = 1;
a = 2; - BB reads value written by A
Example:
a = 1;
b = a; - CB write to a location read by A
Example:
b = a;
a = 1;
- AB write to visible location written by A
12Consider the variables a and b. An anti dependency is defined as A<B (Instruction A immediately precedes B) if
- AB write to a location read by A
Example:
b = a;
a = 1; - BB reads value written by A
Example:
a = 1;
b = a; - CB write to visible location written by A
Example:
a = 1;
a = 2;
- AB write to a location read by A
13[blank_start]Expressing[blank_end] parallelism is how the programmer tells the system that two pieces of code can execute in parallel. [blank_start]Exploiting[blank_end] parallelism is the system actually executing two pieces of code in parallel.
- AExpressing
- BAdding
- CMechanizing
- DConflating
- EEating
- FExploiting
- GRemoving
- HSmelling
- ITangential Execution
14A pipeline hazard exists when
- Athe processor's execution would violate a data or control dependency
- Bthe processor's execution would support a data or control dependency
- Cthe processor's execution would cause a data or control dependency
- Dthe processor's execution would execute a data or control dependency
15We should detect pipeline hazards
- ATrue
- BFalse
16Stalling is one way to handle pipeline hazards
- ATrue
- BFalse
17A [blank_start]pipeline stall[blank_end] is holding an instruction for an extra cycle.
A [blank_start]pipeline bubble[blank_end] is when a pipeline stage is forced to do nothing.- Apipeline stall
- Bpipeline bubble
- Cpipeline hazard
- Dpipeline stage
- Epipeline overhead
18The only data hazards in the Y86 Pipeline are causal hazards on register file
- ATrue
- BFalse
19The only control hazards in the Y86 Pipeline are conditional jumps
- ATrue
- BFalse
20To prevent a data hazard by stalling, we can
- Aread registers in decode that are written by instructions in E, M, or W and then stall the instruction in decode until writer is retired
- Bread registers in fetch that are written by instructions in E, M, or W and then stall the instruction in fetch until writer is retired
- Cread registers in execute that are written by instructions in E, M, or W and then stall the instruction in execute until writer is retired
21How would we resolve a conditional jump control hazard by stalling?
- Astall fetch until jump exits execute
- Bstall execute until jump exits decode
- Cstall fetch and execute until jump exits decode
- Dstall fetch, decode, and execute until jump exits memory
- Estall fetch, decode, execute, and memory until jump exits write back
- Fjust stall everything after fetch indefinitely and go finish off a bottle of wine in one go
22How would we resolve a return control hazard by stalling?
- Astall fetch until return exits memory
- Bstall decode until return exits memory
- Cstall fetch and decode until return exits memory
- Dstall fetch, decode, and execute until return exits memory
- Estall fetch, decode, execute, and memory until return exits memory
- Freturn to cpsc313 in the summer after you fail this midterm
23Check all the statements that are true about the pipeline-control module
- Ait's a hardware component separate from the 5 stages
- Bexamines values across every stage
- Cdecides whether stage should stall or bubble
24 Data forwarding is a mechanism that forwards values from later pipeline stages to earlier ones
- ATrue
- BFalse
25Where does data forwarding forward its data to?
- AD
- BW
- CM
- DE
- EF
26Where does data forward forward its data from?
- AW - new value from memory or ALU
- BM - new value read from memory or from ALU
- CE - new value from ALU
- DD - new value from registers
- EF - new value from PC determined instruction
27Which of these are data hazards?
- Aregister-register hazard
- Bload-use hazard
- Cregister-memory hazard
- Dmemory-memory hazard
- Euse-use hazard
- Fload-load hazard
28Which of these is a register-register hazard?
- Airmovl $1, %eax
addl %eax, %ebx - Birmovl $1, %ecx
addl %eax, %ebx
- Airmovl $1, %eax
29How do we handle a register-register hazard with data forwarding?
- Aforward to D from E, M, or W
- Bforward to F from E, M, or W
- Cstall one cycle, then forward to D from E, M, or W
- Dstall one cycle, then forward to F from D, E, M, or W
- Estall one cycle, then forward to F from E, M, or W
- Fforward to F from D, E, M, or W
30Which of these is a load-use hazard?
- Amrmovl (esi), %eax
addl %eax, %ebx - Brmmovl %eax, (esi)
addl %eax, %ebx
- Amrmovl (esi), %eax
31How would we handle a load-use hazard?
- AStall use one cycle, forward to D from M or W
- BStall use one cycle, forward to D from E or M
- CStall use one cycle, forward to E from D, M, or W
- DStall use one cycle, forward to E from M or W
32Jump prediction is not suitable for resolving conditional-jump hazards
- ATrue
- BFalse
33We know whether the jump is taken or not taken once the jump finishes in stage [blank_start]E[blank_end].
- AE
- BD
- CM
- DW
34valC is the address for the jump as if it were [blank_start]taken[blank_end] and valP is the address for the jump as if it were [blank_start]not taken[blank_end].
- Anot taken
- Btaken
35When a mis-predicted jump is in M, what should we do?
- Ashootdown D and E to prevent them from doing damage
- Bshootdown F and D to prevent them from doing damage
- Cshootdown M and W to prevent them from doing damage
36The homework in this course is much too long
- ATrue
- BFalse
37We could avoid stalling in a load-use hazard by forwarding m.valM to the beginning of E
- ATrue
- BFalse
38We could have one fewer bubble in a misprediction if we compute when conditional jump is in M, reading m.bch (the branch condition)
- ATrue
- BFalse
39In regards to static jump prediction, what could the compiler know?
- Aa jump's taken tendency
- Bfor loops, it can decide to use a continue condition or exit condition
- Cfor if statements it might be able to spot error tests
- Dwhat it sees in the program text
40The compiler cares about the ISA's jump predictions
- ATrue
- BFalse
41How do we optimize handling the return hazard?
- AKeep a stack of return addresses for future use
- BGuess the return address based on the value in predPC
- CGuess the return address based on the value in PC
- DGuess the return address based on the valP in D
42Y86 has indirect jumps
- ATrue
- BFalse
43Indirect jumps are needed for polymorphic dispatch
- ATrue
- BFalse
44CPI =
- AtotalCycles / instructionRetiredCycles
- BinstructionRetiredCycles / totalCycles
45What are the tendencies of deeper pipelines?
- Areduce clock period
- Bincrease CPI
- Cmakes stalling harder to avoid
46Which of these are attributes of super-scalar?
- Amultiple pipelines that run in parallel
- Bissue multiple instructions on each cycle
- Cinstructions execute in parallel and can even bypass each other
- Dif I shut my eyes tight enough, will the midterm disappear?
47What does hyper-threading consist of? (Only one of the following is correct)
- AOS loads multiple runnable threads into CPU, usually from the same process
- BCPU does fast switching between threads to hide memory latency
48What is multi-core?
- Amultiple CPUs per chip, each pipelined, super-scalar, etc
- BCPU's execute independent threads from possibly different processes
49How could Mike do this to us?
- ASadism
- BAlso sadism
- CAnd sadism
- DAll of the above
Information
- Description
- Unit 2 of UBC's CS313 course. Get some alcohol.
- Author
- Zim Brightwood
- Language
- English
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