Test
CSA
Este test tiene tipos de pregunta que se abren en el reproductor de siempre.
Preguntas del test (109)
1The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and
typically larger than the L2 cache- AVerdadero
- BFalso
2The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower
and typically larger than the L2 cache- AVerdadero
- BFalso
3Processor can simultaneously work on multiple instructions. How this technique called?
- APipelining
- BBranch prediction
- CData flow analysis
- DSpeculative execution
- ENone of the above
4Moore’s law: “The interconnections on the integrated circuit are much more reliable than
solder connections. With less circuitry on each chip, there are fewer interchip connections”- AVerdadero
- BFalso
5Moore’s law: “There is a reduction in power and cooling requirements”
- AVerdadero
- BFalso
6Moore’s law: “The computer becomes smaller, making it more convenient to place in a
variety of environments”- AVerdadero
- BFalso
7Moore’s law: “Because logic and memory elements are placed closer together on more
densely packed chips, the electrical path length is shortened, decreasing operating speed”- AVerdadero
- BFalso
8Moore’s law: “The cost of a chip has remained virtually unchanged during this period of
rapid growth in density. This means that the cost of computer logic and memory circuitry has
increasing at a dramatic rate”- AVerdadero
- BFalso
9The “natural” unit of organization of memory
- AWord
- BSequential access
- CAddressable units
- DUnit of transfer
- EDirect access
10Memory is organized into units of data, called records; access must be made in a specific
linear sequence- ASequential access
- BWord
- CAddressable units
- DUnit of transfer
- EDirect access
11For random-access memory, this is the time it takes to perform a read or write operation
- AAccess time
- BMemory cycle time
- CTransfer rate
- DPerformance
- EAll of the above
12A state in which data requested for processing by a component or application is found in the
cache memory- ACache hit
- BCache miss
- CCache set
- DCache overwrites
- ECache access time
13The basic element of a semiconductor memory is:
- AMemory cell
- BCache memory
- CRAM
- DDRAM
- ENone of the above
14RAID stands for
- ARedundant Array Independent Disk
- BRandom Access Integral Disk
- CRedundant Access Integral Disk
- DRandom Array Independent Disk
- ERedundant Access Independent Disk
15The use of the _______ defines the third generation of computers
- ASmall and medium-scale integration
- BTransistor
- CVacuum tube
- DLarge-scale integration
- EVery-large-scale integration
16The use of the _______ defines the first generation of computers.
- AVacuum tube
- BTransistor
- CSmall and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
17The use of the _______ defines the second generation of computers.
- ATransistor
- BVacuum tube
- CSmall and medium-scale integration
- DLarge-scale integration
- EVery-large-scale integration
18Contains the address of the next instruction pair to be fetched from memory
- AProgram counter (PC)
- BMemory buffer register (MBR)
- CMemory address register (MAR)
- DInstruction register (IR)
- EInstruction buffer register (IBR)
19Employed to hold temporarily the right-hand instruction from a word in memory
- AInstruction buffer register (IBR)
- BMemory buffer register (MBR)
- CMemory address register (MAR)
- DInstruction register (IR)
- EProgram counter (PC)
20Contains the 8-bit opcode instruction being executed
- AInstruction register (IR)
- BMemory buffer register (MBR)
- CMemory address register (MAR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
21Specifies the address in memory of the word to be written from or read into the MBR
- AMemory address register (MAR)
- BMemory buffer register (MBR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
22Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word
from memory or from the I/O unit- AMemory buffer register (MBR)
- BMemory address register (MAR)
- CInstruction register (IR)
- DInstruction buffer register (IBR)
- EProgram counter (PC)
23ENIAC stands for:
- AElectronic Numerical Integrator and Computer
- BElectronic Nuclear Integrator and Computer
- CEncapsulation Numerical Integrator and Commerce
- DEncapsulation Numerical Integrator and Computer
- EElectronic Numerical Integer and Computer
24Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance
of processors.- AVerdadero
- BFalso
25A processor is driven by a clock with a constant frequency f or, equivalently, a constant
cycle time t, where t = 1/f:- AInstruction execution rate
- BInstruction execution cycle
- CInstruction execution time
- DInstruction execution period
- ENone of the above
26The time between pulses called?
- ACycle time
- BClock speed
- CClock rate
- DClock cycle
27Typically all operations performed by a processor begin with the:
- Apulse of the clock
- Bpulse of the processor
- Cit begins by itself
- Dboth of clock and processor pulse
- Enone of the above
28Operations performed by a processor, such as fetching an instruction, decoding the
instruction, performing an arithmetic operation, and so on, are governed by:- Aa system clock
- Ba system processor
- Ca clock processor
- Da processor
- Ea clock
29How many categories of process management are there?
- A3
- B2
- C4
- D5
- E1
30Choose the correct answer for the following definition "multiple processes on a system with
a single processor"- AMultiprogramming
- BMultiprocessing
- CDistributed processing
31Choose the correct answer for the following definition "multiple processes on a system with
multiple processors"- AMultiprocessing
- BMultiprogramming
- CDistributed processing
32Choose the correct answer for the following definition "multiple processes on multiple
systems"- ADistributed processing
- BMultiprogramming
- CMultiprocessing
33Parallelism is interleaving of processes in time to give the appearance of
simultaneous execution- AVerdadero
- BFalso
34Concurrency offers genuine simultaneous execution
- AVerdadero
- BFalso
35In concurrency, sharing global resources safely is difficult
- AVerdadero
- BFalso
36In concurrency, locating programming errors can't be difficult, because the
contexts in which errors occur cannot always be reproduced easily- AVerdadero
- BFalso
37In concurrency optimal allocation of resources is difficult
- AVerdadero
- BFalso
38Choose the correct answer for the following definition "When one process is inside a critical
section of code, other processes must be prevented from entering that section"- AMutual exclusion
- BSemaphores
- CMonitors
- DMessage passing
- ECritical section
39 How many approaches of mutex implementation are there?
- A3
- B4
- C2
- D5
- E1
40We can implement mutex through the OS or using programming languages
- AVerdadero
- BFalso
41When using semaphores, processes communicate using messages
- AVerdadero
- BFalso
42How many policy conditions for deadlock to be possible are there?
- A3
- B4
- C2
- D5
- E1
43What is the deadlock?
- APermanent blocking of a set of processes that either compete for global resources or
communicate with each other - BInterleaving of processes in time to give the appearance of simultaneous execution
- CWhen one process is inside a critical section of code, other processes must be prevented from
entering that section - DProcesses “communicate” via global counters that are initialized to a positive integer and that
can be accessed only through two atomic operations
- APermanent blocking of a set of processes that either compete for global resources or
44Deadlock occurs when each process in the set is blocked awaiting an event that
can be triggered only by another blocked process in the set- AVerdadero
- BFalso
45In which of the following approaches there is no shared data?
- AMessage passing
- BMutual exclusion
- CMonitors
- DSemaphores
46Choose the correct answer for the following definition "Synchronization between processes
is defined by the blocking policy attached to the sending and receiving of messages"- AMessage passing
- BMutual exclusion
- CMonitors
- DSemaphores
47Monitors are similar to classes in java and has methods and fields
- AVerdadero
- BFalso
48In atomic operations semSignal(x) and semWait(x), what is the 'x'?
- AThe number of processes that can execute critical section
- BThe number of processes
- CThe number of monitors
- DNo correct answer
49Choose the correct answer for the following definition "Only one process may use a resource
at one time"- AMutual exclusion
- BCircular wai
- CNo preemption
- DHold and wait
50Choose the correct answer for the following definition "A process may hold some resources
while waiting for others"- AHold and wait
- BMutual exclusion
- CCircular wait
- DNo pre-emption
51Choose the correct answer for the following definition: "No process can be forced to release
a resource"- ANo preemption
- BMutual exclusion
- CHold and wait
- DCircular wait
52Choose the correct answer for the following definition "A closed chain of processes exists,
such that each process is blocked waiting for a resource held by another process in the set"- ACircular wait
- BMutual exclusion
- CNo preemption
- DHold and wait
53There are 4 approaches of dealing with deadlock
- AVerdadero
- BFalso
54Choose the correct approach for the following definition "adopting a static policy that
disallows one of the four conditions above"- ADeadlock prevention
- BDeadlock detection and recovery
- CDeadlock avoidance
55Choose the correct approach for the following definition "involves making dynamic choices
that guarantee prevention"- ADeadlock avoidance
- BDeadlock prevention
- CDeadlock detection and recovery
56Choose the correct approach for the following definition "involves recognizing when
deadlock has occurred, and trying to recover"- ADeadlock detection and recovery
- BDeadlock avoidance
- CDeadlock prevention
57There are 2 policies of deadlock prevention
- AVerdadero
- BFalso
58There are 3 approaches of deadlock avoidance
- AVerdadero
- BFalso
59How many deadlock recovery algorithms are there?
- A4
- B3
- C2
- D1
- E5
60In assembly statement name and comment are mandatory
- AVerdadero
- BFalso
61Which keyword you should use in order to define a constant in assembly language
- AEQU
- BDD
- CCONST
- DEQ
- EDW
62There is no memory allocated for constants in assembly language
- AVerdadero
- BFalso
63Choose the definition of stack segment in assembly
- AA block of memory to store a stack
- BAll variable definitions
- CContains a program’s instructio
64Choose the definition of data segment in assembly
- AAll variable definitions
- BA block of memory to store a stack
- CContains a program’s instructions
65Choose the definition of code segment in assembly
- AContains a program’s instructions
- BA block of memory to store a stack
- CAll variable definitions
66Choose the correct syntax of variable declaration in assembly
- Avariable_name type initial_value
- Btype variable_name initial_vaule
- Cvariable_name type initial_value(? )
- Dtype initial_value variable_name
67In assembly language, you can skip the name of variable
- AVerdadero
- BFalso
68Which symbol you should use to leave the variable uninitialized
- A?
- B!
- C@
- D$
69You should use a radix symbol in order to differentiate between binary, octal or
hexadecima- AVerdadero
- BFalso
70 In assembly language you can express data only in binary and decimal
- AVerdadero
- BFalso
71An instruction may have one or more operands
- AVerdadero
- BFalso
72 In two-operand instruction, the first operand is source and the second operand is
destination- AVerdadero
- BFalso
73Choose the legal name(s) in assembly
- A@variable_name
- Bvariable?
- Cvariable&name
- Dvariable name
- E1variable
74Name field of assembly statement is not case sensitive
- AVerdadero
- BFalso
75The assembler translates names into memory addresses
- AVerdadero
- BFalso
76Choose the correct syntax of assembly statements
- Aname operation operand(s) comments
- Boperation name operand(s) comments
- Coperation operand(s) name comment
- Dcomments name operation operand(s)
77Choose the correct answer for the following characteristics: 1. Depend mainly on its
peripherals 2. Used for a few dedicated functions 3. Usually used as a part of a larger system- AMicrocontroller
- BGeneral purpose microprocessor
78Which of the following architectures differs by memory accessing?
- AVon Neumann
- BHarvard
- CComplex Instruction Set Computers
- DReduced Instruction Set Computers
79Choose the characteristics of Harvard architecture
- Aseparate program and data memories
- Bseparated buses allow one instruction to execute while the next instruction is fetched
- Cdata and instructions mustn’t have the same width
- Done memory for data and program
- ECPU provides address to get data or instruction
- Fdata and instructions must have the same width
80Choose the characteristics of Von Neumann architecture
- Aone memory for data and program
- BCPU provides address to get data or instructions
- Cdata and instructions must have the same width
- Dseparate busses, can be accessed simultaneously
- Eseparated buses allow one instruction to execute while the next instruction is fetched
- Fdata and instructions mustn’t have the same width
81Controls the operation of the computer and performs its data processing functions
- AMain memory
- BI/O
- CCPU
- DSystem interconnection
82What provides storage internal to the CPU?
- ARegisters
- BArithmetic and logic unit
- CCPU interconnection
- DControl unit
83ENIAC stands for:
- AElectronical Numerical Integrator And Computer
- BElectronic Numerical Integration Analogue Computer
- CElectronic Numerical Integrator And Computer
- DElectronic Numerical Interaction And Calcuation
84How the central termination point for data channels, the CPU, and memory is called. It schedules
access to the memory from the CPU and data channels, allowing these devices to act independently- ATransistor
- BMultiplexor
- CIntegrated circuit
- DResistors
- ECapacitors
85Expand the abbreviation VLSI
- AVery-large-scale integration
- BVery-little-scale integratio
- CVery-large-scale interactions
- DVery-large-scale integrator
86Which technique allows to processor simultaneously work on multiple instructions?
- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
87 Using this technique processor looks ahead in the instruction code fetched from
memory and predicts which groups of instructions are likely to be processed next.- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
88Which technique helps to processor investigates which instructions are dependent
on each other’s results, or data, to create an optimized schedule of instructions- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
89This technique enables the processor to keep its execution engines as busy as
possible by executing instructions that are likely to be needed.- ABranch prediction
- BData flow analysis
- CPipelining
- DSpeculative execution
90The world’s first general-purpose microprocessor. It was used in the first personal
computer, the Altair.- A8070
- B8080
- C8086
- D8090
91Which of the following laws deals with the potential speedup of a program using
multiple processors compared to a single processor- AMoor’s Law
- BLittle’s Law
- CMurphy's law
- DAmdahl’s law
92The processor responds by suspending operation of the current program, branching
off to a program to service that particular I/O device, known as _________________,
and resuming the original execution after the device is serviced. Which of the
following will be the missing word:- Ainterrupt handler
- Binterrupt cycle
- Cdisabled interrupt
- Dinterrupt request
93What is the data line?
- Aprovide a path for moving data among system modules
- Bis used to designate the source or destination of the data on the data bus
- Cis used to control the access to and the use of the data and address lines
- Dindicates that a module needs to gain control of the bus
94What is used to manage the access to and the use of the data and address lines?
- Aaddress bus
- Bcontrol lines
- Cmemory write
- Dbus grant
- Eaddress lines
95Bus lines can be separated into two generic types:
- ADedicated
- BCentralized
- CDistributed
- DMultiplexed
- ESynchronous
- FAsynchronous
96PCI stands for:
- APower Control Interface
- BPeripheral component interconnect
- CProperty Casualty Insurers
- DProgrammable Communications Interface
97The methods of accessing units of data:
- ASequential access
- BPseudo access
- CDirect access
- DIndirect access
- ESingle access
- FRandom access
- GAssociative access
98What kind of memory type stores data using virtual addresses:
- ALogical
- BVirtual
- CPeripheral
- DMain
- EBuffer
99Amdahl’s law:
- ASpeed up= 1/(1 + f ) * f/N
- BSpeed up= 1/(1 - f ) * f/N
- CSpeed up= 1/(1 - f ) - f/N
- DSpeed up= 1/(1 - f ) + f/N
- ESpeed up= 1/(1 + f ) + f/N
100AMAT stands for:
- AAverage memory access time
- BAutomatic Message Accounting Transmitter
- CAsymptotic Mean Acquisition Time
- DAbsolute memory access time
101_____________ is a special purpose system that is used to perform one or few
dedicated functions.- ADistributed systems
- BEmbedded systems
- CUltra-Large-Scale Systems
- DCentralized systems
- EUbiquitous systems
102How many generations semiconductor memory has been through, since 1970?
[blank_start](please write number)[blank_end]- A13
103MIC stands for:
- Amini integrated core
- Bmany integrated core
- Cmain integrated core
- Dmany interaction core
- Emain interaction core
104Clock Frequency of SDRAM is equal to:
- A200
- B600
- C300
- D166
- E156
105An instruction pipeline increases the performance of a processor by overlapping the
processing of several different instructions. How many stages it is consist of:- A6
- B3
- C5
- D7
- E4
106._____________ is the amount of time it takes the program to perform in seconds
- AElapsed time
- BOverall time
- CEstimate time
- DExecution time
- EProcess time
107How many number systems are exist?
- A4
- B3
- C2
- D1
- E5
108Basic memory elements hold only two states: Zero / One
- AVerdadero
- BFalso
109Which of the following is the right result for this operation: 11001+110001=
- A10101010
- B10101110
- C01001010
- D01100110
- E10001010
Información
- Descripción
- CSA
- Autor
- Dina Taskara
- Idioma
- English
- Visitas
- 5
- Valoración
- Aún sin valoraciones Valora este test