Chapter 7 : Pipelining & RISC

Chapter 7 : Pipelining & RISC

1. Pipelining Hazard

   • Data hazard -occurs when there is conflict in the access of an operand location
     • Type of data hazard -RAW,WAR,WAW
       • Resourse hazard -occurs when 2/more instruction that are already in pipeline read at the same resourse
         • Control hazard (branch hazard) -occurs when the pipeline makes wrong decision

2. Pipelining of unequal stages

   • Always take the largest of the stage delay to be the cycle time
     • No stage overlaps & the latency must be constant
       • Ensure the instruction overlap is the same as the cycle time

3. RISC

   • Simple instruction format
     • Register to register operation
       • One machine instruction per machine cycle
         • Simple addressing mode

4. Instruction Execution Characteristics

   • Operation performed
     • Execution Sequencing
       • Semantic gap
         • Opreand used
           • high-level language

5. 6 Types of Additional stages

   • Fetch instruction (FI)
     • Decode instruction (DI)
       • Calculate operand (CO)
         • Fetch operand (FO)
           • Execute instruction (EI)
             • Write operand (WO)

6. Timing Diagram

   • n=numbers of instruction
     • k=stages
       • T=seconds

7. Pipelining

   • Multiple tasking operating simultaneously using in diffrent resourse
     • Doesn't help latency of single task,it help throughput of entire work load
       • Allows execution of multiple instruction to overlap time