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Preguntas del test (80)
11. What is Temporal Locality?
- Aa. items whose addresses are near one another tend to be referenced close together in time
- Bb. the nearest data stored in secondary memory
- Cc. recently accessed items are likely to be accessed in the near future
22. For completing programmer's desire for unlimited quick memory, suggested economical solution was
- Aa. Temporal locality
- Bb. Spatial locality
- Cc. Memory hierarchy
33. In Non-Blocking Caches what does mean "Early restart"?
- Aa. Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- Bb. Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
4Design issue of interconnection network
- Aa. RLP
- Bb. Software Cost
- Cc. Symmetry of the network
- Dd. Hardware Cost
5What is a hash table?
- Aa. Popular data structure for organizing a large collection of data items so that one can quickly answer questions
- Bb. Popular data structure for updating large collections, so that one can hardly answer questions
- Cc. Popular tables for organizing a large collection of data structure
- Dd. Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
6Convert given number using sign-magnitude representation from decimal to binary number system. Decimal number: - 5
- Aa. 1101
- Bb. 1011
- Cc. 0101
7The "natural" unit of organization of memory
- Aa. Several Computer
- Bb. Word
- Cc. Document
8How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?:
- Aa. 4
- Bb. 3
- Cc. 2
9What is the MISD one of the categories of computers?:
- Aa. Multiple Instruction Streams, Set Data Stream
- Bb. Multiple Instructions Streams, Single Data Stream
- Cc. Multiple Instruction Streams, Multiple Data Streams
10How many Optimizations' in Cache memory Performance?
- Aa. 8
- Bb. 6
- Cc. 10
11The second type of dependence is ?
- Aa. Control dependence
- Bb. Name dependence
- Cc. Data dependence
12What is the Thread Level Parallelism -
- Aa. Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- Bb. Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
- Cc. Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
13What is a Node degree?
- Aa. It is the minimum distance between the farthest nodes in a network
- Bb. Number of edges connected with a node is called node degree
- Cc. It indicates how the nodes a network are organized
14The most popular scheme is set associative, where a set is?
- Aa. a group of comparatives
- Bb. a group of blocks
- Cc. a group of instructions
15What is the ROB?
- Aa. Relocate buffer
- Bb. Reorder buffer
- Cc. Read only buffer
16What is the "Module reliability" in Dependability?
- Aa. a measure of the interruption
- Bb. a measure of the continuous service accomplishment from a reference initial instant
- Cc. a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
17What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- Aa. n loop iterations
- Bb. subroutine call
- Cc. vector access
18Desktop benchmarks divide into __ broad classes:
- Aa. two
- Bb. three
- Cc. four
- Dd. five
19At VLIW by "performance and loop iteration" which time is longer?
- Aa. Software Pipelined
- Bb. Loop Unrolled
20The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
- Aa. If the block placement strategy is not fully associative
- Bb. If the cache cannot contain all the blocks needed during execution of a program
- Cc. The very first access to a block cannot be in the cache, so the block must be brought into the cache
21Select two independent dimensions of the Operating System
- Abatch and interactive
- Bb. batch and computer operator
- Cc. Interactive and computer operator
22Perfect caches at The Hardware Model?
- Aa. All memory addresses are known exactly
- Bb. All conditional branches are predicted exactly
- Cc. All memory accesses take one clock cycle
23How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
- Aa. Error detection and response
- Bb. Controlled access to files
- Cc. System access Неверно
24Convert given number using sign-magnitude representation from decimal to binary number system. Decimal number (use 8 bit): -18
- Aa. 1001 0010
- Bb. 1001 0011
- Cc. 0001 0010
25The two basic forms of semiconductor random access memory are
- Aa. dynamic RAM (DRAM) and static RAM (SRAM
- Bb. Winchester and optical disks
- Cc. magnetic and optical
26How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs...
- Aa. Program execution
- Bb. Access to I/O devices
- Cc. Program creation
27Convert given number using sign-magnitude representation from decimal to binary number system. Decimal number (use 16 bit): -150
- Aa. 1000 0000 1001 0110 Верно
- Bb. 0000 0000 1001 0110
- Cc. 0001 0000 1001 0110
28Total amount of work done in a given time , such as megabytes per second for disk transfer...
- Aa. performance
- Bb. latency
- Cthroughput
- Dbandwidth
29A logical cache stores data using ...
- Aa. Physical addresses
- Bb. virtual addresses
- Cc. virtual addresses and physical addresses
30At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- Aa. Speculative operations that don't cause exceptions
- Bb. Allow one instruction to branch multiple directions
31What is the Increasing cache bandwidth?
- Aa. Pipelined caches, multibanked caches, and nonblocking caches
- Bb. Small and simple first-level caches and way-prediction
- Cc. Critical word first and merging write buffer
32Select the Pentium Memory Management Parameter according to this description. Indicates whether write-through or write-back caching policy will be used for data in the corresponding page.
- Aa. Page Write Through bit (PWT) Верно
- Bb. program Read/Write bit (RW)
- Cc. Present bit (P)
33Different types of parallelism in applications like:
- Aa. Data-Level Parallelism
- Bb. All above
- Cc. Task-Level Parallelism
- Dd. Instruction-Level Parallelism
34What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
- Aa. True sharing misses
- Bb. False sharing misses
35In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
- AComputing
- BMultithreading
- Cc. Array processing
36What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Aa. vector access
- Bb. subroutine call
- Cc. n loop iterations
37If a block can be placed at every location in cache, this cache is said to be?
- Aa. Fully associative
- Bb. Indirectly mapped
- Cc. Directly mapped
38Virtual memory producing virtual-addresses, are translated by
- Aa. All above
- Bb. Logical addresses
- Cc. Physical addresses
- Dd. Local addresses
39Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
- Aa. Cacheable (C) bit
- Bb. Type Extension (TEX)
- Cc. Bufferable (B) bit
40... can be removed and replaced with another disk.
- Aa. Processor registers
- Bb. A removable disk
- Cc. A nonremovable disk
41What is the Instruction Level Parallelism:
- Aa. Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- Bb. Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
- Cc. Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
42Products that are sold by multiple vendors in large volumes and are essentially identical
- Aa. boxes
- Bb. commodities
- Cc. folders
- Dd. files
43What is the Reducing the Miss Rate?
- Aa. Performance Optimization
- Bb. Time Optimization
- Cc. Compiler Optimization
44Shared Memory...
- Aa. A logically discrete section of computational work
- Bb. Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
- Cc. From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
45How many functions at Integrated Instruction Fetch Units
- Aa. 4
- Bb. 3
- Cc. 5
46For what the reorder buffer is used :
- Aa. To pass parameters through instructions that may be speculated
- Bb. To get additional registers in the same way as the reservation stations
- Cc. To pass results among instructions that may be speculated.
- Dd. To control registers
47The data will not go from the port registers to the pin unless:
- Aa. DDR register of that port is set to 1
- Bb. PORT register of that port is set to 0
- Cc. DDR register of that port is set to 0
48Select the Pentium Memory Management Parameter according to this description. This bit is set to 1 by the processor in both levels of page tables when a read or write operation to the corresponding page occurs.
- Aa. Dirty bit (D)
- Bb. S bit
- Cc. Accessed bit (A)
49How many classes of computers classified?
- Aa. 5
- Bb. 3
- Cc. 7
50What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Aa. vector access
- Bb. n loop iterations
- Cc. subroutine call
51To initialise any port as an output port what value is to be given to it?
- Aa. 0x01
- Bb. A port is by default an output port
- Cc. 0x00
- Dd. 0xFF
52A number of chips can be grouped together to form ...
- Aa. a memory linis
- Bb. a memory tags
- Cc. a memory bank
53The effectiveness of the cache memory is based on the property of ________
- Aa. Memory size
- Bb. Locality of reference
- Cc. Memory localization
54What functions has Instruction Set Architecture (ISA)?
- Aa. Serves as the bridge between CPU and Cache
- Bb. Serves as the boundary between the software and hardware?
- Cc. Serves as the bridge between CPU and Memory
55Which one is not the major flavor of Multiple-issue processors:
- Aa. statically scheduled superscalar processors
- Bb. statistically superscalar processors
- Cc. dynamically scheduled superscalar processors
- Dd. VLIW (very long instruction word) processors
56Pipelining ...
- Aa. Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
- Bb. A logically discrete section of computational work
- Cc. From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
57Select the Pentium Memory Management Parameter according to this description. Provides the physical address of the page in memory if the present bit is set. Since page frames are aligned on 4K boundaries, the bottom 12 bits are 0, and only the top 20 bits are included in the entry. In a page directory, the address is that of a page table.
- Aa. Granularity bit (G)
- Bb. S bit
- Cc. Page Frame Address
58What is the PMD in computer classes?
- Aa. Peak maze development
- Bb. Powerful markup distance
- Cc. Personal mobile device
- Dd. Percentage map device
59General categories of instructions' operation are
- Aa. Arithmetic logical
- Bb. All above
- Cc. Data transfer
- Dd. floating point
60Which one is NOT concerning to pitfall?
- Aa. Over emphasizing memory bandwidth in DRAMs
- Bb. Predicting cache performance of one program from another
- Cc. Simulating enough instructions to get accurate performance measures of the memory hierarchy
- Dd. Implementing a virtual machine monitor on an instruction set architecture that wasn't designed to be virtualizable
61What is the Request Level Parallelism:
- AExploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- BExploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- CExploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
62How many possible Elements of Data Hazards?
- A3
- B6
- C8
63What is the Reducing the Hit time?
- ACritical word first and merging write buffer
- BSmall and simple first-level caches and way-prediction
- CPipelined caches, multibanked caches, and nonblocking caches
64Select internal memory ...
- AProcessor registers
- BCD-ROM
- CHard Disk
65Select the Pentium Memory Management Parameter according to this description: Specifies the privilege level of the segment referred to by this segment descriptor.
- ASegment Present bit (P)
- BDescriptor Privilege Level (DPL)
- CAccessed bit (A)
66Examples of VLIW processor
- AMIPS and ARM
- BItanium
- CPentium 4, MIPS R12K, IBM, Power5
- DTI C6x
67When single-processor performance improvement has dropped?
- A2004
- B2003
- C2002
68What is a Latency?
- AIt indicates how the nodes a network are organized
- BIt is the delay in transferring the message between two nodes
- CIt is the minimum distance between the farthest nodes in a network
69If we want to sustain four instructions per clock
- AWe must fetch more, issue less, and initiate execution on more than three instructions
- BWe must fetch more, issue more, and initiate execution on more than four instructions
- CWe must fetch more, issue more, and initiate execution on less than five instructions
- DWe must fetch less, issue more, and initiate execution on more than two instructions
70The important function of the Operating System is
- AIncrease size of cache
- BProvide compiler for high level programming languages
- CMemory management
71Select multi-dimensional interconnection network
- ACross Bar
- BLinear Array
- CCube
72Per memory reference, miss-rate can be turned into per instruction misses rate by
- AMiss rate= Memory accesses+ instructions
- BMiss rate= Memory accesses* instructions
- CMiss rate= Memory accesses-instructions
- DMiss rate= Memory accesses/ instructions
73Select correct memory hierarchy:
- AProcessor registers - Cache memory - Main memory
- BCache memory - Main memory - Processor registers
- CCache memory - Processor registers - Main memory
74At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called "Shared" in a simple protocol?
- AExactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- BNo processor has a copy of the cache block
- COne or more processors have the block cached, and the value in memory is up to date
75Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
- AVirtual memory
- BCache miss
- CCache hit
- DRead back
76How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
- ASystem access
- BControlled access to files
- CAccounting
77What is a Data transfer time?
- AThe data routing functions are the functions which when executed establishe the path between the source and the destination
- BHow long does it take for a message to reach to another processor
- CIt indicates how the nodes a network are organized
- DIt is an indicative measure of the message carrying capacity of a network
78What is the Conflict in main categories in Cache Memory?
- Acache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Bfirst-reference to a block, occur even with infinite cache
- Cmisses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
79For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
- Asingle sided
- Bdouble sided
- Cno sides
80Set of instructions examined as candidates for potential execution is called the
- ACube
- BFrame
- CWindow arsen kotak
Información
- Descripción
- Test sobre Arch, creado por Арсен Жаксыгул el 11/12/2017.
- Autor
- Арсен Жаксыгул
- Idioma
- English
- Visitas
- 29
- Valoración
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