Test
PC Architecture
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Preguntas del test (190)
1In 32-bit addressing mode, address field is either 1 byte or?
- Ao 4 bytes
- Bo 2 bytes
- Co 6 bytes
2If a block can be placed at every location in cache, this cache is said to be?
- Ao Fully associative
- Bo Directly mapped
- Co Indirectly mapped
3Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?
- Ao Write-through
- Bo Write-back
- Co Miss rate
4Average access time of memory for having memory-hierarchy performance is given as?
- Ao Average memory access time = Hit time - Miss rate
- Bo Average memory access time = hit time + (miss rate and miss penalty)
- Co Average memory access time = Hit time + Miss rate - Miss penalty
5As segment or a page is normally used for block, page-fault and address-fault is used for
- Ao Hit
- Bo Miss
- Co Cache
- Do Stack
6Virtual memory producing virtual-addresses, are translated by
- Ao Logical addresses
- Bo Physical addresses
- Co Local addresses
- Do All above
7Per memory reference, miss-rate can be turned into per instruction misses rate by
- Ao Miss rate= Memory accesses* instructions
- Bo Miss rate= Memory accesses/ instructions
- Co Miss rate= Memory accesses-instructions
- Do Miss rate= Memory accesses+ instructions
8Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
- Ao Read back
- Bo Cache miss
- Co Virtual memory
- Do Cache hit
9For reducing frequency on replacement of write-back blocks, commonly used feature, is known as
- Ao Hit miss
- Bo Index field
- Co Dirty bit
- Do Write-through
10If cache is not able for containing all blocks needed while execution, miss is then known as
- Ao Hit miss
- Bo Cache hit
- Co Cache miss
- Do Hit rate
11!ISPRAVIT OTVET! For completing programmer's desire for unlimited quick memory, suggested economical solution was
- Ao Memory hierarchy ISPRAVIT OTVET!
- Bo Temporal locality ISPRAVIT OTVET!
- Co Spatial locality ISPRAVIT OTVET!
12An instruction that does no operation for changing state is known as
- Ao Nope
- Bo No
- Co NOP
13Set of instructions examined as candidates for potential execution is called the
- Ao Frame
- Bo Cube
- Co Window
14Different types of parallelism in applications like:
- Ao Data-Level Parallelism
- Bo Task-Level Parallelism
- Co Instruction-Level Parallelism
- Do All above
15Term 'computer architecture' is sometimes referred only to
- Ao Instruction set design
- Bo Circuit design
- Co Hardware design
16General categories of instructions' operation are
- Ao Data transfer
- Bo Arithmetic logical
- Co floating point
- Do All above
17The effectiveness of the cache memory is based on the property of ________
- Ao Locality of reference
- Bo Memory localization
- Co Memory size
18The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
- Ao Level 2 cache
- Bo Level 1 cache
- Co Registers
19The last on the hierarchy scale of memory devices is ______.
- Ao Main memory
- Bo Branch
- Co Secondary memory
20In the memory hierarchy, as the speed of operation increases the memory size also increases
- Ao True
- Bo False
21!ISPRAVIT OTVET! A common measure of performance is
- Ao Price/performance ratio.
- Bo Performance/price ratio
- Co Operation/price ratio.
22The number successful accesses to memory stated as a fraction is called as _____
- Ao Miss rate
- Bo Hit rate
- Co Access rate
23With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as
- Ao Scalability
- Bo Module availability
- Co Module reliability
24From a reference initial instant, a measure of service accomplishment. is known as
- Ao Module reliability
- Bo Hardware
- Co Sector
25To initialize any port as an output port what value is to be given to it?
- Ao A port is by default an output port
- Bo 0x01
- Co 0x00
- Do 0xFF
26In AVR, which registers are there for the I/O programming of ports?
- Ao PORT
- Bo PIN
- Co DDR
- Do all above
27The data will not go from the port registers to the pin unless:
- Ao DDR register of that port is set to 0
- Bo DDR register of that port is set to 1
- Co PORT register of that port is set to 0
28What is the file extension that is loaded in a micro controller for executing any instruction?
- Ao .doc
- Bo .hex
- Co .txt
29What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?
- Ao True sharing misses
- Bo False sharing misses
30What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
- Ao False sharing misses
- Bo True sharing misses
31At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?
- Ao One or more processors have the block cached, and the value in memory is up to date
- Bo Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- Co No processor has a copy of the cache block
32At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?
- Ao No processor has a copy of the cache block
- Bo Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
- Co One or more processors have the block cached, and the value in memory is up to date
33In Non-Blocking Caches what does mean “Early restart”?
- Ao Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
- Bo Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
34!ISPRAVIT OTVET! Far more sophisticated techniques are possible What is a Latency:
- Ao is time for a single access – Main memory latency is usually >> than processor cycle time
- Bo is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
- Co is amount of data that can be in flight at the same time (Little’s Law)
35!ISPRAVIT OTVET! What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
- Ao n loop iterations
- Bo subroutine call
- Co vector access
36!ISPRAVIT OTVET! What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
37!!!!!!!!!!!!!!!!!What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
- Ao subroutine call
- Bo n loop iterations
- Co vector access
38!!!!!!!!!!!!!!!!!!!!!!!!!!!!What is kernel process?
- Ao Provide at least two modes, indicating whether the running process is a user process or an operating system process
- Bo Provide at least five modes, indicating whether the running process is a user process or an operating system process
- Co Provide a portion of the processor state that a user process can use but not write
- Do None of them
39Which one is NOT concerning to pitfall?
- Ao Predicting cache performance of one program from another
- Bo Simulating enough instructions to get accurate performance measures of the memory hierarchy
- Co Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- Do Over emphasizing memory bandwidth in DRAMs
40Which one is concerning to fallacy?
- Ao Predicting cache performance of one program from another
- Bo Simulating enough instructions to get accurate performance measures of the memory hierarchy
- Co Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
- Do Over emphasizing memory bandwidth in DRAMs
41@@@@@@@@@@At VLIW by “performance and loop iteration” which time is longer?
- Ao Loop Unrolled
- Bo Software Pipelined
42@@@@@@@@@@At VLIW by “performance and loop iteration” which time is shorter?
- Ao Software Pipelined
- Bo Loop Unrolled
43@@@@@@At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
- Ao Speculative operations that don’t cause exceptions
- Bo Hardware to check pointer hazards
44@@@@At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
- Ao Hardware to check pointer hazards
- Bo Speculative operations that don’t cause exceptions
45@@@@At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
- Ao Allow one instruction to branch multiple directions
- Bo Speculative operations that don’t cause exceptions
46In Multilevel Caches “Local miss rate” equals =
- Ao misses in cache / accesses to cache
- Bo misses in cache / CPU memory accesses
- Co misses in cache / number of instructions
47In Multilevel Caches “Global miss rate” equals =
- Ao misses in cache / CPU memory accesses
- Bo misses in cache / accesses to cache
- Co misses in cache / number of instructions
48In Multilevel Caches “Misses per instruction” equals =
- Ao misses in cache / number of instructions
- Bo misses in cache / accesses to cache
- Co misses in cache / CPU memory accesses
49Network performance depends of what?
- Ao performance of switches and transmission system
- Bo performance of switches
- Co performance of transmission system
- Do has no dependencies
50The time between the start and the completion of an event ,such as milliseconds for a disk access is...
- Ao latency
- Bo bandwidth
- Co throughput
- Do performance
51Total amount of work done in a given time , such as megabytes per second for disk transfer...
- Ao bandwidth
- Bo latency
- Co throughput
- Do performance
52Products that are sold by multiple vendors in large volumes and are essentially identical
- Ao commodities
- Bo boxes
- Co folders
- Do files
53Integrated circuit processes are characterized by the
- Ao feature size
- Bo permanent size n
- Co complex size
- Do fixed size
54Manufacturing costs that decrease over time are ____
- Ao the learning curve
- Bo the cycled line
- Co the regular option
- Do the final loop
55Volume is a ________ key factor in determining cost.
- Ao second
- Bo first
- Co fifth
- Do third
56The most companies spend only ____________ of their income on R&D, which includes all engineering.
- Ao 4% to 12%
- Bo 15% to 30%
- Co 1% to 17%
- Do 30% to 48%
57Desktop benchmarks divide into __ broad classes:
- Ao two
- Bo three
- Co four
- Do five
58A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
- Ao 90% 10%
- Bo 50% 50%
- Co 70% 30%
- Do 89% 11%
59(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
- Ao Speedup
- Bo Efficiency
- Co Probability
- Do Ration
60@@@@@@@@Which of the following descriptions corresponds to static power?
- Ao Grows proportionally to the transistor count (whether or not the transistors are switching)
- Bo Proportional to the product of the number of switching transistors and the switching rate Probability
- Co Proportional to the product of the number of switching transistors and the switching rate
- Do All of the above
61@@@@@@@@@If we want to sustain four instructions per clock
- Ao We must fetch more, issue more, and initiate execution on more than four instructions
- Bo We must fetch less, issue more, and initiate execution on more than two instructions
- Co We must fetch more, issue less, and initiate execution on more than three instructions
- Do We must fetch more, issue more, and initiate execution on less than five instructions
62What is a hash table?
- Ao Popular data structure for organizing a large collection of data items so that one can quickly answer questions
- Bo Popular data structure for updating large collections, so that one can hardly answer questions
- Co Popular tables for organizing a large collection of data structure
- Do Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
63How this process called: “Operations execute as soon as their operands are available”
- Ao data flow execution
- Bo instruction execution
- Co data control execution
- Do instruction field execution
64For what the reorder buffer is used :
- Ao To pass results among instructions that may be speculated.
- Bo To pass parameters through instructions that may be speculated
- Co To get additional registers in the same way as the reservation stations
- Do To control registers
65Which one is not the major flavor of Multiple-issue processors:
- Ao statistically superscalar processors
- Bo dynamically scheduled superscalar processors
- Co statically scheduled superscalar processors
- Do VLIW (very long instruction word) processors
66Examples of superscalar(static):
- Ao MIPS and ARM
- Bo Pentium 4, MIPS R12K, IBM, Power5
- Co Itanium
- Do TI C6x
67Examples of superscalar(dynamic) :
- Ao None at the present
- Bo Pentium 4, MIPS R12K, IBM, Power5
- Co MIPS and ARM
- Do TI C6x
68Examples of VLIW processor:
- Ao TI C6x
- Bo MIPS and ARM
- Co Itanium
- Do Pentium 4, MIPS R12K, IBM, Power5
69Which is not the function of integrated instruction fetch unit:
- Ao Instruction memory commit
- Bo Integrated branch prediction
- Co Instruction prefetch
- Do Instruction memory access and buffering
70What is a topology in interconnection networks?
- Ao It indicates how the nodes a network are organised
- Bo It is the minimum distance between the farthest nodes in a network
- Co Number of edges connected with a node is called node degree
71What is a Network Diameter?
- Ao It is the minimum distance between the farthest nodes in a network
- Bo It indicates how the nodes a network are organized
- Co Number of edges connected with a node is called node degree
72What is a Node degree?
- Ao Number of edges connected with a node is called node degree
- Bo It indicates how the nodes a network are organized
- Co It is the minimum distance between the farthest nodes in a network
73What is a Bisection Bandwidth?
- Ao It indicates how the nodes a network are organized
- Bo Number of edges required to be cut to divide a network into two halves is called bisection bandwidth
- Co It indicates how the nodes a network are organized
- Do It is the minimum distance between the farthest nodes in a network
74What is Latency?
- Ao It indicates how the nodes a network are organized
- Bo It is the delay in transferring the message between two nodes
- Co It indicates how the nodes a network are organized
- Do It is the minimum distance between the farthest nodes in a network
75What is a Hardware Cost?
- Ao It indicates how the nodes a network are organized
- Bo The data routing functions are the functions which when executed establishe the path between the source and the destination
- Co It refers to the cost involved in the implementation of an interconnection network
- Do It is an indicative measure of the message carrying capacity of a network
76What is a Blocking and Non-Blocking network?
- Ao It indicates how the nodes a network are organized
- Bo The data routing functions are the functions which when executed establishe the path between the source and the destination
- Co network In non-blocking networks the route from any free input node to any free output node can always be provided
- Do It is an indicative measure of the message carrying capacity of a network
77Design issue of interconnection network
- Ao Dimension and size of network
- Bo Broadcast and Multicast
- Co Hardware Cost
- Do RLP
78Design issue of interconnection network
- Ao Software Cost
- Bo Hardware Cost
- Co RLP
- Do Symmetry of the network
79What is a Data transfer time?
- Ao It indicates how the nodes a network are organized
- Bo The data routing functions are the functions which when executed establishe the path between the source and the destination
- Co How long does it take for a message to reach to another processor
- Do It is an indicative measure of the message carrying capacity of a network
80Select two-dimensional interconnection network
- Ao Mesh
- Bo Linear Array
- Co Cross Bar
81Select multi-dimensional interconnection network
- Ao Linear Array
- Bo Cross Bar
- Co Cube
82Select multi-dimensional interconnection network
- Ao Linear Array
- Bo Cross Bar
- Co Hyper Cube
83Select non-blocking interconnection network
- Ao Linear Array
- Bo Cube
- Co CrossBar
84A modified version of the tree interconnection network
- Ao Fat tree
- Bo Cube
- Co Linear Array
85A interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
- Ao Systolic Array
- Bo Cube
- Co Linear Array
86A _____________ interconnection network is an extension of cube network
- Ao Hyper Cube
- Bo Cube
- Co Linear Array
87In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
- Ao Multithreading
- Bo Computing
- Co Array processing
88Select two-dimensional interconnection network
- Ao Linear Array
- Bo Mesh
- Co Cross Bar
89Single Instruction, Single Data (SISD)
- Ao Only one instruction stream is being acted on by the CPU during any one clock cycle
- Bo A type of parallel computer
- Co Currently, the most common type of parallel computer - most modern supercomputers fall into this category
90@@@@@@@90. In Parallel Computing
- Ao Executed on a single processor
- Bo A problem is broken into discrete parts that can be solved concurrently
- Co A problem is broken into a discrete series of instructions
91Pipelining …
- Ao Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
- Bo A logically discrete section of computational work
- Co From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
92@@@@@@@@@@92. Shared Memory…
- Ao From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
- Bo A logically discrete section of computational work
- Co Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
93What is a RISC computers?
- Ao Reduced Instruction Set Computer
- Bo Rational Interruptible Security Computer
- Co Research Interconnect Several Computer
94When single-processor performance improvement has dropped?
- Ao 2003
- Bo 2004
- Co 2002
95How much in percentage single-processor performance improvement has dropped to less than?
- Ao 22%
- Bo 11%
- Co 33%
96@@@@@@@@96. How many classes of computers classified?
- Ao 3
- Bo 7
- Co 5
97What is the PMD in computer classes?
- Ao Percentage map device
- Bo Powerful markup distance
- Co Peak maze development
- Do Personal mobile device
98@@@@@@@@@98. What is the Thread Level Parallelism -
- Ao Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
- Bo Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- Co Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
99@@@@@@@@99. What is the Request Level Parallelism:
- Ao Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
- Bo Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
- Co Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
100What is the Instruction Level Parallelism:
- Ao Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
- Bo Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
- Co Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
101What is the MISD one of the categories of computers?:
- Ao Multiple Instruction Streams, Multiple Data Streams
- Bo Multiple Instructions Streams, Single Data Stream
- Co Multiple Instruction Streams, Set Data Stream
102How many elements in Trends of Technology?
- Ao 6
- Bo 5
- Co 4
103How many elements of the Instruction Set Architecture (ISA):
- Ao 8
- Bo 7
104How many types of dependencies do you know?
- Ao 4
- Bo 5
- Co 3
105How many possible Elements of Data Hazards?
- Ao 6
- Bo 3
- Co 8
106What is the “ISSUE” in Pipelining Basics?
- Ao Decode instructions, check for data hazard
- Bo Decode instructions, check for structural hazard
- Co Decode instructions, check for control hazard
107What is the “Read Operands” in Pipelining Basics?
- Ao Wait until no control hazards, then read operands
- Bo Wait until no structural hazards, then read operands
- Co Wait until no data hazards, then read operands
108How many Optimizations’ in Cache memory Performance?
- Ao 8
- Bo 10
- Co 6
109What is the Compulsory in main categories in Cache Memory?
- Ao cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Bo misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Co first-reference to a block, occur even with infinite cache
110What is the Capacity in main categories in Cache Memory?
- Ao first-reference to a block, occur even with infinite cache
- Bo cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
- Co misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
111What is the Conflict in main categories in Cache Memory?
- Ao first-reference to a block, occur even with infinite cache
- Bo misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
- Co cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
112What is the Temporal Locality?
- Ao Exploit by fetching blocks of data around recently accessed locations
- Bo Exploit by remembering the contents of recently accessed locations
113What is the Spatial Locality?
- Ao Exploit by remembering the contents of recently accessed locations
- Bo Exploit by fetching blocks of data around recently accessed locations
114What is the Reducing the Hit time?
- Ao Pipelined caches, multibanked caches, and nonblocking caches
- Bo Small and simple first-level caches and way-prediction
- Co Critical word first and merging write buffer
115What is the Increasing cache bandwidth?
- Ao Small and simple first-level caches and way-prediction
- Bo Critical word first and merging write buffer
- Co Pipelined caches, multibanked caches, and nonblocking caches
116What is the Reducing the Miss Penalty?
- Ao Small and simple first-level caches and way-prediction
- Bo Pipelined caches, multibanked caches, and nonblocking caches
- Co Critical word first and merging write buffer
117What is the Reducing the Miss Rate?
- Ao Compiler Optimization
- Bo Time Optimization
- Co Performance Optimization
118Main term of dependability is SLAs?
- Ao Standard level achievement
- Bo Scale level approach
- Co Service level agreements
119Main term of dependability is SLOs?
- Ao Standard level offset
- Bo Service level objectives
120The second type of dependence is?
- Ao Data dependence
- Bo Name dependence
- Co Control dependence
121RAW (read after write)?
- Ao This hazard corresponds to an output dependence
- Bo This hazard arises from an antidependence (or name dependence)
- Co This hazard is the most common type and corresponds to a true data dependence
122WAW (write after write)?
- Ao This hazard is the most common type and corresponds to a true data dependence
- Bo This hazard arises from an antidependence (or name dependence)
- Co This hazard corresponds to an output dependence
123WAR (write after read)?
- Ao This hazard corresponds to an output dependence
- Bo This hazard arises from an antidependence (or name dependence)
- Co This hazard is the most common type and corresponds to a true data dependence
124What is the element “Read Operands” in simple five-stage pipeline?
- Ao Decode instructions, check for structural hazards
- Bo Wait until no data hazards, then read operands
125What is the ROB?
- Ao Reorder buffer
- Bo Read only buffer
- Co Relocate buffer
126How many steps in instruction execution?
- Ao 6
- Bo 5
- Co 3
- Do 4
127How many restrictions RAW hazards through memory are maintained?
- Ao 2
- Bo 3
- Co 4
128How many major flavors in Multiple-issue processors?
- Ao 3
- Bo 4
- Co 5
129How many functions at Integrated Instruction Fetch Units
- Ao 3
- Bo 4
- Co 5
130Speculation and the Challenge of Energy Efficiency consume excess energy in how many ways?
- Ao 2
- Bo 3
- Co 4
131The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
- Ao 5
- Bo 4
- Co 6
132Infinite register renaming at The Hardware Model?
- Ao Branch prediction is perfect, all conditional branches are predicted exactly
- Bo There are an infinite number of virtual registers available
133Perfect caches at The Hardware Model?
- Ao All memory addresses are known exactly
- Bo All memory accesses take one clock cycle
- Co All conditional branches are predicted exactly
134Perfect memory address alias analysis at The Hardware Model?
- Ao All memory accesses take one clock cycle
- Bo All memory addresses are known exactly
- Co All conditional branches are predicted exactly
135Perfect jump prediction at The Hardware Model?
- Ao All conditional branches are predicted exactly
- Bo All memory addresses are known exactly
- Co All jumps are perfectly predicted
136What is Personal mobile device (PMD)?
- Ao A collection of computers with wireless network adapters
- Bo A collection of Clusters/Warehouse-scale computers
- Co A collection of wireless devices with multimedia user interfaces
137Where the embedded microprocessors are used?
- Ao In Personal Computers
- Bo In microwaves, washing machines
- Co In mobile phones
138What functions has Instruction Set Architecture (ISA)?
- Ao Serves as the boundary between the software and hardware?
- Bo Serves as the bridge between CPU and Memory
- Co Serves as the bridge between CPU and Cache
139What is the TLP?
- Ao Time Level Parallelism
- Bo Technology Level Parallelism
- Co Task Level Parallelism
140By Moore's law, growth rate in transistor count on a chip is doubling?
- Ao every 8 to 12 months
- Bo every 12 to 16 months
- Co every 18 to 24 months
141How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?:
- Ao 2
- Bo 4
- Co 3
142What is the “Module reliability” in Dependability?
- Ao a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
- Bo a measure of the continuous service accomplishment from a reference initial instant
- Co a measure of the interruption
143What is response time?
- Ao The time to get an information
- Bo The time spent on execution of a program
- Co the time between the start and the completion of an event
144The guiding principle of reporting performance measurements should be?
- Ao repro¬ducibility
- Bo responsibility
- Co creativity
145What is Temporal Locality?
- Ao items whose addresses are near one another tend to be referenced close together in time
- Bo recently accessed items are likely to be accessed in the near future
- Co the nearest data stored in secondary memory
146What is Spatial Locality?
- Ao recently accessed items are likely to be accessed in the near future
- Bo items whose addresses are near one another tend to be refer¬enced close together in time
- Co the nearest data stored in secondary memory
147What is Amdahl's law?
- Ao Defines time spent on execution of a program
- Bo Defines the speedup that can be gained by using a particular feature
- Co Defines data gained in one operation
148The most popular scheme is set associative, where a set is?
- Ao a group of instructions
- Bo a group of blocks
- Co a group of comparatives
149The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
- Ao The very first access to a block cannot be in the cache, so the block must be brought into the cache
- Bo If the cache cannot contain all the blocks needed during execution of a program
- Co If the block placement strategy is not fully associative
150The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
- Ao The very first access to a block cannot be in the cache, so the block must be brought into the cache
- Bo If the cache cannot contain all the blocks needed during execution of a program
- Co If the block placement strategy is not fully associative
151The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
- Ao The very first access to a block cannot be in the cache, so the block must be brought into the cache
- Bo If the block placement strategy is not fully associative
- Co If the cache cannot contain all the blocks needed during execution of a program
152The “natural” unit of organization of memory
- Ao Document
- Bo Several Computer
- Co Word
153Main element of cache memory is …
- Ao Word
- Bo Line
- Co String
154Typical levels of Cache memories …
- Ao 1,2,3 levels
- Bo 1,2,3,4,5 levels
- Co Cache memories have no levels
155Select internal memory …
- Ao Hard Disk
- Bo CD-ROM
- Co Processor registers
156Select internal memory
- Ao Hard Disk
- Bo Optical disk
- Co Main memory
157Select internal memory
- Ao Cache
- Bo Magnetic tape
- Co Optical disks
158Select external memory?
- Ao Processor registers
- Bo Cache
- Co Main memory
- Do Hard disks
159Select external memory
- Ao Optical Disk
- Bo Cache level 1
- Co Registers of processor
160Select external memory
- Ao Magnetic tape
- Bo Main memory
- Co All cache memories
161Physical types of memories:
- Ao Direct, Random
- Bo Direct, Access time
- Co Semiconductor, Optical
162Physical types of memories:
- Ao Semiconductor, Magnetic
- Bo Word, Block
- Co Direct, Random
163Physical types of memories:
- Ao Magneto-optical
- Bo Number of words
- Co Number of bytes
164Select correct memory hierarchy:
- Ao Secondary storages - Cache – Main Memory
- Bo Cache – Main Memory – Secondary storages
- Co Main Memory – Cache - Secondary storages
165Select correct memory hierarchy:
- Ao Cache memory – Main memory - Processor registers
- Bo Cache memory – Processor registers - Main memory
- Co Processor registers – Cache memory – Main memory
166External, nonvolatile memory is also referred to as …
- Ao Main memeory
- Bo auxiliary memory
- Co Levels of cache
167Types of cache addresses
- Ao Direct, Associative
- Bo Logical, Physical
- Co Set Associative
168A logical cache stores data using …
- Ao virtual addresses
- Bo virtual addresses and physical addresses
- Co Physical addresses
169The two basic forms of semiconductor random access memory are
- Ao magnetic and optical
- Bo dynamic RAM (DRAM) and static RAM (SRAM)
- Co Winchester and optical disks
170Main element of cache memory
- Ao Tag
- Bo Word
- Co String
171A number of chips can be grouped together to form …
- Ao a memory bank
- Bo a memory tags
- Co a memory linis
172Data are recorded on and later retrieved from the disk via a conducting coil named
- Ao The arm
- Bo The slid
- Co The head
173The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
- Ao multiple zoned recording
- Bo intersector gap
- Co the constant angular velocity
174To increase density, modern hard disk systems use a technique known as
- Ao the constant angular velocity
- Bo multiple zone recording
175… can be removed and replaced with another disk.
- Ao Processor registers
- Bo A nonremovable disk
- Co A removable disk
176For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
- Ao double sided
- Bo single sided
- Co no sides
177The set of all the tracks in the same relative position on the platter is referred to as …
- Ao a cylinder
- Bo a square
- Co a circle
178On a movable head system, the time it takes to position the head at the track is known as …
- Ao transfer time
- Bo access time
- Co seek time
179The operating system …
- Ao is the software that controls the execution of programs on a processor and that manages the processor’s resources.
- Bo is one which is understandable by us humans
- Co is a collection of Clusters/Warehouse-scale computers
- Do a program that directly executes instructions written in a programming language
180The most important functions of the Operating System are
- Ao Compile C++ program codes
- Bo The scheduling of processes, or tasks
- Co Interpret PHP program codes
- Do Provide drivers for the remote devices
181The important function of the Operating System is
- Ao Provide compiler for high level programming languages
- Bo Increase size of cache
- Co Memory management
182How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
- Ao Program execution
- Bo Access to I/O devices
- Co Program creation
183How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
- Ao Program creation
- Bo Access to I/O devices
- Co Program execution
184How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
- Ao Access to I/O devices
- Bo Program execution
- Co Program creation
185How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
- Ao Controlled access to files
- Bo Access to I/O devices:
- Co System access
186How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
- Ao Error detection and response
- Bo System access
- Co Controlled access to files
187How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
- Ao System access
- Bo Accounting
- Co Controlled access to files
188Select two independent dimensions of the Operating System
- Ao batch and interactive
- Bo batch and computer operator
- Co Interactive and computer operator
189Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
- Ao Bufferable (B) bit
- Bo Access Permission (AP), Access Permission Extension (APX)
- Co Cacheable (C) bit
190Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
- Ao Bufferable (B) bit
- Bo Cacheable (C) bit
- Co Type Extension (TEX)
Información
- Descripción
- Test sobre PC Architecture, creado por Avatar Avatarov el 10/04/2018.
- Autor
- Avatar Avatarov
- Idioma
- English
- Visitas
- 26
- Valoración
- Aún sin valoraciones Valora este test